SiFive has launched a high-end “P650” core for up to 16-core SoCs that features the latest RISC-V Hypervisor spec, one of 15 that were just ratified by RISC-V Int’l. Meanwhile, Andes speeds up its Linux-friendly AndesCore 45MP and NX27V cores.

In the run up to next week’s RISC-V Summit in San Francisco, several RISC-V organizations have some news to share. SiFive has unveiled a previously teased SiFive Performance P650 CPU core that it claims outperforms Cortex-A77, the Arm architecture used on the Snapdragon 865. The Linux-focused P650 supports the Hypervisor extension, one of 15 new RISC-V specs announced this week by RISC-V International, the Switzerland-based organization that oversees RISC-V. Other Linux-related RISC-V news includes a performance improvement for Andes’ AndesCore 45MP and NX27V cores (see farther below).

SiFive Performance P600 series block diagram
(click image to enlarge)

This week, RISC-V International announced that its membership has grown by 130 percent in 2021. Also this week Deloitte Global released a report (via TechRepublic) that projects that sales of RISC-V processing cores will double in 2022 and double again in 2023 when it will comprise a $800 million market. The number is expected to approach $1 billion in 2024.

The report suggests that while the RISC-V market will continue to boom, driven in part by China’s interest in silicon independence and the lure of lower costs for smaller chip designers. Yet, major chipmakers and hardware manufacturers are not likely to switch their core investments from Arm and Intel any time soon, says Deloitte.

Even SiFive’s new P650 trails the latest Intel and Arm designs, such as Qualcomm’s Snapdragon 8 Gen 1, which was announced this week. The smartphone SoC features the latest Armv9 cores including the high-end Cortex-X2 (16 percent faster than -X1), as well as Cortex-A710 (10 percent faster than -A78), and Cortex-A510 (35 percent faster than -A55). All the Armv9 cores have at least twice the AI power of their predecessors.

Finally, Arm licensees may not jump ship to RISC-V as quickly as planned if Nvidia’s $40 billion acquisition of Arm is derailed. This seems increasingly likely after the FTC sued to block the deal yesterday.

Nevertheless, RISC-V continues to gain ground in areas like automotive and IoT, and the Hypervisor spec and powerful CPU designs like the P650 should start to crack open the datacenter market. RISC-V smartphones could start showing up next year. Sipeed, which recently launched a LicheeRV SBC that runs Linux on an Allwinner D1 RISC-V SoC, has just posted a video showing a RISC-V RV64-powered smartphone prototype running Android 10.

 
SiFive Performance P650

The SiFive Performance P650 “is expected to be the fastest licensable RISC-V processor IP core in the market,” says SiFive. Designed for “data center to edge, automotive, compute, mobile and more, the Cortex-A77 like RISC-V CPU core design builds upon the Cortex-A55 like SiFive Performance P550 processor that launched in June. Although Intel failed to come to terms with SiFive in its bid to acquire it, it appears the companies will continue as partners, and Intel plans to use the P550 in an upcoming, 7nm “Horse Creek” processor.

SiFive Performance P650 architecture
(click image to enlarge)

The SiFive Performance P650, which like the P550 uses SiFive’s latest U8 architecture, “maintains an efficient core pipeline while expanding the processor instruction-issue width to deliver an impressive 40% performance increase per clock cycle” compared to the P550, claims SiFive. “Additional architecture enhancements improve maximum clock frequency, achieving an overall 50% performance gain…with a projected score of 11+ SPECInt2006/GHz.” The design also “maintains a significant performance-per-area advantage” compared to Cortex-A77, says SiFive.

Like the P550, the P650 adopts SiFive’s Arm Big.Little-like mix+match heterogeneous multi-core technology. Yet while the P550 is designed for up to quad-core SoCs, the P650 can drive 16-core SoCs.

Other highlights include a 4-issue, 13-stage out-of-order pipeline, compared to 3-issue for the P550. The core offers private L2 caches and a streaming prefetcher for improved memory performance, and it supports up to 128KB of L1 and up to 4x 256-bit memory ports plus SECDED ECC. The design integrates SiFive WorldGuard security technology and supports cache stashing to L3 “for tightly coupled accelerators,” says SiFive.

 
Hypervisor spec streamlines RISC-V virtualization

The SiFive Performance P650 supports the new RISC-V Hypervisor extension for virtualization. According to RISC-V International, the Hypervisor spec “virtualizes supervisor-level architecture to efficiently host guest operating systems atop a type-1 or type-2 hypervisor.”

RISC-V International notes that hypervisors are not limited to the datacenter. Other applications include automotive and industrial control applications that require isolated hardware. KVM and other open source VMs have been ported “ on top of simulators using the new specification,” says the group.

A report from The Register says the new Hypervisor spec streamlines the “rather clunky” hardware virtualization support in RISC-V. “Hypervisors aware of this extension can create virtualized environments for guests by mapping blocks of physical RAM to RAM inside a virtual machine using pagination, which the guest OS can break up into virtual memory spaces in which user-level programs run,” explains The Register. “This is far more flexible and advantageous in terms of the number of guests that can be juggled by the hypervisor and managing RAM usage of virtual machines, and arguably makes it easier to port hypervisors for other architectures to RISC-V. It also enables kernel-level hypervisors, by virtualizing supervisor-level CPU control registers, as well as supporting bare-metal hypervisors.”

The Register quotes SiFive product marketing VP Chris Jones as saying the company expects the P650 will be seen in 5nm fabricated SoCs, enabling clock rates of 2.7GHz or more.

 
RISC-V International adds 15 RISC-V extension

The Hypervisor spec is just one of 15 new extensions that were ratified this week for up to extensions 40 overall ratified by RISC-V International. The other major new extensions are the Vector and Scalar Cryptography specs.

The Vector extension is the final release of the Vector (RVV) RV64GCV extensions that are supported by several new Linux-ready RISC-V processor designs, such as the recent SiFive Intelligence X280. The spec “will help accelerate the computation of data intensive operations like ML inference for audio, vision, and voice processing,” says RISC-V International. Key applications include “edge computing applications from consumer IoT devices to industrial ML applications.”

The RISC-V Scalar Cryptography spec accelerates cryptographic workloads for small footprint deployments such as IoT and embedded devices. The extensions “allow for implementing standard cryptographic hash and block cipher algorithms that are an order of magnitude faster than using standard instructions in some cases,” stated Ben Marshall, Cryptographic Hardware Engineer at PQShield and member of the RISC-V Technical Steering Committee. “In addition to the performance benefits, these new extensions are very cheap to implement so companies can integrate popular cryptography algorithms in even the smallest connected devices.”

 
Andes speeds up its Linux-powered A(X)45MP and NX27V

Last December, Andes Technology unveiled four new Linux-focused RISC-V cores, including the 32-bit A45MP and a 64-bit AX45MP, which offers support up to 4x cores at up to 2.4GHz. Yesterday, Andes announced performance upgrades for these A(X)45MP cores, as well as a similar upgrade for its RV64GCV enabled NX27V, which is based on the lower-end, Linux-ready A27 series. (SiFive similarly announces performance upgrades of previously announced IP, such as this July’s 21G2 release of its Essential 7-series cores, including the Linux-ready U74.)

AndesCore NX27V block diagram

Compared to the original A(X)45MP cores, the upgraded models “deliver up to 3x memory bandwidth while raising the floating-point performance by over 20 percent as measured by Whetstone benchmark,” says Andes. “The latency for Level-1 Cache miss and Level-2 Cache hit has been reduced by half,” which helps to enable 3.4 SPECint2006/GHz performance, says the company. The upgrade also integrates the RISC-V trace interface and debug spec.

The edge AI oriented NX27V, meanwhile, has been upgraded with full configurations of 128-bit to 512-bit VLEN/SIMD/MEM. For vector data types, the NX27V now implements FP16 to FP64 and Int8 to Int64, as well as Andes-enhanced BF16 and Int4 for optimized AI data representations. With the all 512-bit configuration, the NX27V “can achieve over 98x speedup comparing with pure C program and 66% higher performance for MobileNet-v1 benchmark than the all 256-bit configuration,” says Andes.

 
Further information

The SiFive Performance P650 Architecture Preview will be offered to lead customers in Q1 of 2022, with general availability coming mid-year. A dev kit will be available with RTL eval, test bench RTL, SDK, FPGA bitstream, and documentation. More information may be found in SiFive’s announcement and P650 product page.

More on the 15 new RISC-V extensions may be found in RISC-V International’s announcement and Specifications page.

More on the Andes core speedups may be found in its announcement.