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Renesas reveals its first 32-bit RISC-V CPU

Nov 30, 2023 — by Giorgio Mendoza 340 views

Renesas Electronics recently announced the release of its first 32-bit CPU core based on the RISC-V open-standard instruction set architecture (ISA). This development represents Renesas’ entry into the RISC-V based market. The new CPU core will be compatible with Renesas’ e2 studio IDE, in addition to supporting third-party IDEs tailored for RISC-V based MCUs, facilitating a range of development applications.

RISC-V Advantage:

RISC-V, an open ISA, is becoming increasingly popular for its flexibility, scalability, power efficiency, and open ecosystem. Renesas, diverging from the trend of forming joint investment alliances, has independently developed a versatile RISC-V core. This core can be used as a primary application controller, a secondary core in SoCs, on-chip subsystems, or in deeply embedded ASSPs, demonstrating its adaptability across various applications.


Technical Innovations:

The Renesas RISC-V CPU stands out for its efficiency, flexibility, and computational throughput. It allows implementers to choose between the RV32 ‘I’ or ‘E’ options, optimizing the number of general-purpose registers based on the application. Moreover, it integrates several ‘extensions’, such as the M extension for optimized multiplication and division, the A extension for atomic access instructions, the C extension for compressed instructions, and the B extension for bit manipulation. These features enable the CPU to balance power consumption, performance, and silicon footprint effectively.

Enhanced Features:

The CPU includes a stack monitor register to detect and prevent stack memory overflows, a dynamic branch prediction unit to improve code execution throughput, and a compact JTAG debug interface. Additionally, the implementation of several performance monitor registers and an instruction tracing unit offers developers deeper insights into system behavior.

Renesas RISC-V core block diagram
(click image to enlarge)

Performance and Development Tools:

Achieving a remarkable 3.27 CoreMark/MHz performance, the Renesas RISC-V CPU outperforms similar architectures. The CPU’s features have been validated in real silicon product implementation, showcasing impressive benchmarks. Developers can leverage the Renesas e2 studio environment or major commercial third-party IDEs supporting RISC-V based MCUs, ensuring a comprehensive toolchain for product development.

Further information

For more information on the Renesas product announcement, refer to the provided link. Additional specifics regarding the performance score will be available on the EEMBC website following the unveiling of the first product in early 2024 according to Renesas.

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