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GOWIN & Andes Technologies collaborate and reveal 22nm SoC FPGA

Sep 2, 2023 — by Giorgio Mendoza 411 views

Gowin Semiconductor and Andes Technologies have recently unveiled the specifications for their AndesCore A25 RISC-V CPU IP along with the AE350 peripheral subsystem integrated into the GW5AST-138 GOWIN FPGA from the Arora V family.

The announcement marks one of the initial successful implementations of a complete RISC-V MCU implemented into an FPGA. This achievement enables designers to leverage the A25 processor and its essential peripherals without consuming FPGA resources.

GW5AST Series architecture
(click image to enlarge)

GOWIN mentions the following: “In the Arora V family, we incorporate the peripherals that a RISC-V CPU typically requires in hard instantiations. We included a fully controllable high-speed SerDes for communication, video aggregation, and AI computing acceleration applications that demand very high data rates. Other instantiated functions include Block RAM modules supporting ECC error correction, high-performance multiple voltage GPIO, and high accuracy clock architecture. These hard functions save the FPGA programmable fabric of up 138K LUT’s for the designers’ unique logic implementation.”

GW5AST-138 Bank Distribution view
(click image to enlarge)

These are some of the specifications of the RISC-V based GW5AST-138 FPGA:

  • AndesCore A25 Hard Core:
    • Operating Frequency: 400MHz
    • Support for RISC-V P-extension DSP/SIMD ISA (draft)
    • Single- and double-precision floating-point instructions
    • Bit-manipulation instructions
    • MMU for Linux-based applications
  • AE350 AXI/AHB-Based Platform:
    • Level-one memories
    • Interrupt controller
    • Debug module
    • AXI and AHB Bus Matrix Controller
    • AXI-to-AHB Bridge
    • Collection of fundamental AHB/APB bus IP components pre-integrated as a system design
    • DDR3 controller and SPI-Flash controller in the FPGA fabric
  • Memory Hierarchy:
    • A25’s 32KByte I-Cache and D-Cache
    • Off-chip DDR3 for data memory
    • SPI-Flash contains A25’s instruction memory (codes copied from SPI-Flash into DDR3 and Cache upon boot-up)
  • GOWIN GW5AST-138 FPGA Fabric:
    • 138K LUTs for custom design implementation
    • Supports custom logic design alongside hard instantiated functions
  • GOWIN EDA (Arora V Development Environment):
    • Provides an easy-to-use FPGA hardware development environment
    • Supports multiple RTL-based programming languages
    • Synthesis, placement, and routing capabilities
    • Bitstream generation and download tools
    • Power analysis tools
    • In-device logic analyzer support

GW5AST-138 resources
(click image to enlarge)

The table above describes some of the resources available in the GW5AST-138. For additional technical information refer to the datasheet found here.

Andes Technology and GOWIN logos
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Further information

GOWIN indicates  that the “GW5AST-138 FPGA with SDK with GOWIN_V1.9.9 Beta-3 will be available August 18 through distribution.” Visit the product announcement for more details.

(advertise here)

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