The program provides participants with practical exposure to RISC-V computer architecture, guiding them in creating and compiling C and RISC-V assembly code for the RVfpga SoC.

Furthermore, participants will acquire hands-on experience in tailoring the microarchitecture of the SweRV EH1 Core, investigating its diverse functions using performance counters and established benchmarks.

 

The course provides practical labs that can be conducted through simulation using tools like RVfpga-Whisper, Verilator, or RVfpga-VidBo. These labs can also be executed on hardware by utilizing the Nexys A7 development board, which is built on a Xilinx Artix-7 FPGA.

• XC7A100T-1CSG324C – 15,850 Logic slices, 4,860 Block RAM (Kbits), 128 DDR2 Memory (MiB); 6 Clock Tiles (with PLL), 240 DSP Slices; 450MHz internal clock frequency

The course syllabus includes coverage of the following topics:

• Chapter 1. Installation and Initial Demonstrations
• Chapter 2. C Programming with the RVfpga SoC
• Chapter 3. RISC-V Assembly Programming with the RVfpga SoC
• Chapter 4. RISC-V Function Calls
• Chapter 5. Mixing C and Assembly Functions in a Program
• Chapter 6. Introduction to Peripherals and Input/Output
• Chapter 7. More I/O: 7-Segment Displays
• Chapter 8. More I/O: Timers
• Chapter 9. Interrupts
• Chapter 10. Delving Deeper into the RISC-V VeeR Core

The announcement suggests that users should possess a foundational understanding of the following topics:

• Digital logic design
• High-level programming (e.g., C programming)
• Assembly programming
• RISC-V instruction set architecture
• Processor microarchitecture
• Memory and input/output systems.”

Further information

While the class can be audited for free like most edX courses, users have the option to obtain a certificate for $126.65 (usually priced at $149.00). For further details, see the announcement and the edX course page. Additionally, users can explore other useful RISC-V courses in the Learning Path section on this page.