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Andes’ RISC-V SoC debuts with AI-ready VPU as Microchip opens access to its PolarFire SoC

Dec 10, 2019 — by Eric Brown 1,799 views

[Updated: Dec. 11] — Andes unveiled a Linux-ready, RISC-V-based “AndesCore 27-series” CPU core that features a VPU for AI applications. In other RISC-V on Linux news, Microchip opened early access to its FPGA-enabled PolarFire SoC and Hex Five announced MultiZone Security for Linux.

In conjunction with the RISC-V Summit in San Jose this week, Andes Technology announced a Linux-focused RISC-V core design that it says is the first to include a vector processing unit (VPU). Meanwhile, Microchip announced an early access program for its previously announced, Linux-friendly PolarFire SoC. (Since this story was published we have updated it with info on an upcoming “Icicle” dev board for the SoC.) Finally, there’s a new MultiZone Security for Linux application for RISC-V chips from Hex Five Security that will initially run on the PolarFire SoC (see farther below).

The RISC-V phenomenon shows no sign of tapering off. Aside from being open source and customizable, one of the main benefits of the architecture is that it is fully modern and unburdened with legacy code.


SiFive has been an early leader in the Linux-focused side of the market, along with Andes and other players such as Alibaba with its 16-core XT910 core. In October, SiFive announced a next-gen, Linux-friendly U8-Series Core IP that is roughly equivalent to Arm’s Cortex-A72.
Earlier this year, the Linux Foundation launched a Chips Alliance to develop open source code for RISC-V chip development. RISC-V’s success has also encouraged imitators, such as Wave Computing open source MIPS core IP. Arm has responded to the RISC-V threat by opening up its proprietary architecture somewhat with its Custom Instructions extension and Arm Flexible Access licensing program.
AndesCore 27-series
Andes Technology has released an AndesCore 27-series CPU core to an unnamed early customer. The new IP is claimed to be “the first licensable RISC-V core to deliver to a production licensee the RISC-V Vector instruction extension (RVV).” The first 27-series cores will be the 32-bit A27 and 64-bit AX27 and NX27V cores, which will enter production in Q1 2020.

The cores build on the foundation of the previous A25 and AX25 cores, as well as the DSP-enabled A25MP and AX25MP variants we covered back in March. The 27-series has a rearchitected memory subsystem compared to the 25-series, delivering 50 percent higher memory bandwidth.

Andes NX27V (left) and NX27V VPU architectures
(click images to enlarge)

Only the NX27V includes the RVV-driven vector processing unit (VPU), but it otherwise appears to be identical to the AX27. Andes describes the VPU as a “Cray-like full vectorization computation unit” that is more powerful than incremental SIMD instruction extensions found on other RISC-V designs.

The VPU enables applications that require complex computation of large volumes of matrix data, such as AI, AR/VR, computer vision, cryptography, and multimedia processing, says Andes. The RVV-enabled VPU enables a “powerful instruction set with scalable data sizes, and flexible microarchitecture implementations, and leaves memory subsystem decisions open for system level optimization,” says the company.
The NX27V’s VPU contains a Vector Register File (VRF) that contains a user-configurable number of elements per register. Each vector can be arbitrary in length, ranging from 64-bit to 512-bit (VLEN), or even to 4096-bit by combining up to eight vector registers (LMUL). Each computation of integer, fixed point, floating point, or other AI-optimized representations can be any bit-width, ranging from 4- to 32-bit (SEW). The VPU can handle non-divisible last matrix elements in the same loop.

The VPU has multiple, chainable functional units that can operate in independent pipelines, thereby enabling throughputs required by critical kernel functions. It can achieve over 30x speedup on key functions in the MobileNets convolution neural network (CNN), claims Andes.

The memory subsystem improvements on all three AndesCore 27-series cores support “multiple outstanding memory accesses inflight” to eliminate CPU and VPU wait times for data during cache misses, says the company. Cache pre-fetches also help to negate potential cache misses. Andes has also enhanced its Andes Custom Extension (ACE) interface to provide instruction customization.

Andes had no further details on the cores, but since they are based closely on the earlier A25 and AX25, we can expect the same 5-stage pipeline and support for up to 1.2GHz, 3.5 CoreMark/MHz performance. It does not appear that they offer a DSP like the otherwise identical MP versions. The new 27-series cores use the same development tools as the A25/AX25, including an AndeSight IDE, a “COPILOT” tool for ACE, and JTAG and ICE debugging. (For more details, see our earlier A25MP and AX25MP report.)
Microchip opens PolarFire SoC for early access
Microchip’s early access program will allow qualified customers to use its Linux-compatible “Mi-V” RISC-V ecosystem development tools to get started on the PolarFire SoC prior to the production release in Q3 2020. These include Microchip’s Libero SoC 12.3 FPGA design suite and the embedded focused SoftConsole 6.2 IDE. Debug is supported with a Renode virtual model.

PolarFire SoC architecture
(click image to enlarge)

As we reported a year ago when Microchip’s Microsemi unit unveiled its low power, real-time deterministic PolarFire SoC architecture, the SoC combines its PolarFire FPGA with 4x RISC-V U54-MC CPU cores supplied by SiFive. The PolarFire SoC’s chief advantages over hybrid Arm/FPGA SoCs such as the Xilinx Zynq and Intel Stratix 10 include a more customizable, open RISC-V design, as well as lower power consumption and much better real-time deterministic capabilities, says Microchip.

A year ago, Microchip said the PolarFire SoC would “bring real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core CPU cluster.” In today’s announcement, the company said it was “the first SoC FPGA with a deterministic, coherent RISC-V CPU cluster and a deterministic L2 memory subsystem enabling Linux plus real-time applications.”

PolarFire SoC

The PolarFire SoC uses a modified version of SiFive’s 28nm fabricated, 960MHz to 1.5GHz U54-MC quad-core complex, which also powers SiFive’s Freedom U540 SoCs on its HiFive Unleashed board. Branch predictors have been deactivated to enable more deterministic behavior, among other changes.

The PolarFire SoC inherits the extensive security and reliability features of the PolarFire FPGA. These include single and double error correction and double error detection (SEC-DED) on all memories.

Mi-V ecosystem partners supporting the PolarFire SoC include Wind River, Mentor Graphics, WolfSSL, ExpressLogic, Veridify, FreeRTOS, and Hex Five (see farther below). IAR systems and AdaCore will also provide development tools. Today, Wind River announced RISC-V support for its recently upgraded VxWorks RTOS.
PolarFire SoC Icicle Kit
(Update: After we published this story, CNXSoft reported that a Linux-driven “Icicle” development platform will be available next year for the PolarFire SoC that costs only a “few hundred dollars.” By comparison, the previously announced development kit, which combines SiFive’s HiFive Unleashed SBC and Microchip’s HiFive Unleashed Expansion Board, cost $2,000.

The PolarFire SoC Icicle Kit, which is still under development, will include LPDDR4 “x32,” as well as QSPI and eMMC flash, says CNXSoft. For communications, the board will supply WiFi, Bluetooth and 2x Gigabit Ethernet ports. Other features are said to include HDMI 2.0, micro-USB 2.0 OTG, and micro-USB debug ports.

A 40-pin Raspberry Pi compatible expansion header will provide GPIO, I2C, SPI, and UART, and a PCIe connector will support USB 2.0, UART, SPI, I2C, CAN, and HDMI 2.0. The Icicle will be further equipped with JTAG, 4x LEDs, 4x buttons, and a power sensor.)
MultiZone Security for Linux
Hex Five Security, which also goes as “Hex-Five,” announced a security platform it calls the first “enclave” for RISC-V “designed to bring security through separation to embedded systems.” The new MultiZone Security for Linux is available now for Microchip’s PolarFire SoC. This “hardened real-time, Linux capable, RISC-V-based microprocessor subsystem” will support other RISC-V processor “later in 2020.”

MultiZone Security for Linux architecture working with SiFive U54 cores
(click image to enlarge)

MultiZone Security for Linux provides “hardware-enforced software-defined separation for multiple execution domains with full control of data, programs and peripherals,” says Hex Five. Unlike a hypervisor-based solution, the software doesn’t require hardware support for virtualization or changes to existing application software, says the company.

The initial PolarFire SoC version is optimized to orchestrate the PolarFire FPGA’s many security hardware blocks, including its physical memory protection, defense-grade secure boot, and a crypto core said to be resistant to differential power analysis, Earlier MultiZone Security packages include an IoT Stack version aimed at FreeRTOS-based RISC-V solutions.
Further information
The AndesCore 27-series 32-bit A27 and 64-bit AX27 and NX27V cores will enter production in Q1 2020. More information may be found in Andes Technology’s AndesCore 27-series announcement.
The PolarFire SoC early access program (EAP) has begun now with full production due in Q3 2020. More information may be found in Microchip’s PolarFire SoC EAP announcement.
Hex Five’s MultiZone Security for Linux is available now for the PolarFire SoC with other versions coming later in 2020. More information may be found in its
announcement and MultiZone Security for Linux product page.

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