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SiFive unleashes the first Linux-ready, 64-bit RISC-V SoC

Oct 4, 2017 — by Eric Brown 4,286 views

SiFive has taped out the first multi-core RISC-V based processor design, and the first to run Linux, featuring 4x 1.5GHz “U54” cores and a management core.

SiFive announced “early access” availability of the 64-bit, quad-core U54-MC Coreplex – the first Linux-ready application processor built around the open source RISC-V architecture. Fabricated with a TSMC’s 28nm HPC process, the real-time capable U54-MC Coreplex is the first multi-core RISC-V design, and the first to offer cache coherence. The processor is intended for AI, machine learning, networking, gateways and smart IoT devices. A development board is set to ship in Q1 2018.

U54-MC Coreplex block diagram
(click image to enlarge)

The U54-MC Coreplex combines four “U54” cores and a “E51” management core. The U54 cores support the RV64GC ISA, “which is expected to be the standard for Linux-based RISC-V devices,” says SiFive. The U54 cores clock from between 960MHz to 1.5GHz, although there’s also mention of 1.7 DMIPS/MHz and 2.75 CoreMark/MHz performance.

Each of the 0.234mm square U54 cores features a “highly efficient” five-stage in-order pipeline, and has 32KB L1 instruction and data caches. All the cores share a coherent 2MB L2 cache. Real-time capabilities are enabled by the fact that both the L1 instruction and L2 caches can be configured into high speed deterministic SRAMs, says SiFive.


Other features include a debug with trace and a “CLINT” unit for multi-core timer and software interrupts. There’s also a “PLIC” with support for up to 511 interrupts with 7x priority levels.

There are no GPUs or other co-processors in the U54-MC Coreplex design, but its customizable nature will enable customers to add their own. SiFive will even work with customers to develop different core configurations aside from its current 4+1 design.

Customers can built peripheral IP with an open source, native TileLink interface bus. This “high-performance scalable cache-coherent fabric” is available with bridge adapters for legacy bus protocols such as AXI4, AHB-Lite, and APB, says SiFive.

The U54-MC Coreplex is the first silicon release of SiFive’s Freedom Unleashed family of high-end processors, which are compatible with Unix-based operating systems and optimized for Linux. In July 2016, the San Mateo, Calif. based fabless chip designer announced the first Linux-ready Freedom Unleashed design with the octa-core Freedom U500. Instead, SiFive has chosen to start with the similar, but quad-core U54-MC Coreplex.


Aside from being open source and customizable, one of the main benefits of RISC-V is that it is fully modern, purpose built, and unburdened with legacy code. Over the last year, SiFive customers like Microsemi and Arduino have released various RISC-V based MCU chips. SiFive’s initial, 320MHz FE310 MCU based on its original Freedom E300 design, appeared last November in an Arduino ready HiFive1 dev kit. In May, SiFive and Arduino unveiled a wireless-enabled Arduino Cinque board based on SiFive’s HiFive, featuring a RISC-V FE310 SoC and an ESP32 wireless module.

Also in May, SiFive announced free downloads and tools for rapid evaluation of the “fully synthesizable” RISC-V based E31 and E51 Coreplex IP that drives the FE310. The tools were made available on a $99 Digilent Arty FPGA development board.

SiFive’s comparison chart between U54-MC Coreplex and Cortex-A35
(click image to enlarge)

SiFive has posted a chart (see above) that compares the U54-MC Coreplex with Arm’s 64-bit, ARMv8-A based Cortex-A35 IP, which will eventually appear in NXP’s delayed i.MX8. The chart emphasizes U54-MC Coreplex advantages over the Cortex-A35 including real-time capability, support for 16-bit instructions, and the addition of a Physical Memory Protection (PMP) unit in addition to an MMU. Unlike the Cortex-A35, SiFive’s design also includes a built-in interrupt controller and management core instead of requiring additional IP.

Yet, the workhorse ARM design these days is the faster Cortex-A53, which is found on most smartphones, as well as embedded devices such as the Raspberry Pi 3. According to an EETimes story posted this morning, the “single issue” U54 core is expected to lag the performance of the “dual issue” Cortex-A53. The story also reported that the U54-MC Coreplex can be driven at rates up to 2.6GHz at 0.99 V, and that the SoC measures roughly 30mm square.

According to the EETimes, SiFive is offering customers 100 prototype SoCs for $100,000 “with no fees on third-party IP bundled with its cores until customers ship their chips.” The story quotes SiFive VP Jack King as saying: “Today, you pay all the IP costs upfront — we think that’s the wrong way.”

SiFive is supporting the U54-MC Coreplex with “a rich SDK with demo software and an easy-to-install binary toolchain,” says the company. Standard development and debug tools such as OpenOCD, GDB, and an Eclipse IDE, are also available.

Further information

The U54-MC Coreplex is available now in a limited “early access” phase to be followed by greater availability in Q1 2018 when the processor will be available with a development board. A signup page is available for requesting access. More information may be found in SiFive’s U54-MC Coreplex announcement and product page.

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