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Imagination Catapults into RISC-V

Dec 7, 2021 — by Eric Brown 304 views

Imagination unveiled four RISC-V-based “Catapult” CPU cores: two 32-bit MCU cores and two 64-bit designs that run Linux, including an automotive functional safety core.

The big news on the first day of the RISC-V Summit in San Francisco was the announcement from Imagination Technologies that it was launching four RISC-V core designs under a Catapult brand. This summer, Imagination revealed it was building RISC-V CPU cores, and it has now announced four Catapult CPU designs.

The in-order cores include two 32-bit MCU-like cores and two 64-bit models that run Linux. The UK-based company refers to the four core categories as “dynamic microcontrollers; real-time embedded CPUs; high-performance application CPUs; and functionally safe automotive CPUs.”



Catapult block diagram
(click image to enlarge)
(Source: Imagination, via AnandTech)

The 32-bit microcontrollers, which AnandTech says are comparable with Cortex-M, are already shipping as components in Imagination’s automotive GPUs. The real-time designs, which AnandTech pegs as being much like Cortex-R, are designed for high-efficiency embedded applications and are now available for licensing. Single-core, 64-bit cores that run Linux, on par with Cortex-A, will be available in general-purpose and FuSA-enabled automotive versions in 2022.

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Imagination’s Catapult roadmap points to the availability of multi-core ready, in-order IP available in early 2023 and more advanced out-of-order CPU IP by 2024. This will be followed with a Next Generation Heterogenous Compute CPU.

AnandTech suggests the Next Generation core will be its first mainstream CPU design to take on Arm and other more advanced RISC-V players such as SiFive. So far, the other big news at the conference has been a SiFive Performance P650 CPU core, which supports the newly ratified Hypervisor extension. SiFive claims it outperforms Cortex-A77.

Imagination has supplied few details on its cores. Keep in mind that just because a core IP is based on the open-spec RISC-V ISA and perhaps some open RISC-V extensions does not mean the design must be fully revealed.

The multi-threaded cores “can be scaled up to eight asymmetric coherent cores-per cluster for enhanced SoC versatility, with an option to add custom accelerators,” says SiFive. Imagination provides full hardware and software support for building heterogenous SoCs.

A slide posted by AnandTech mentions a robust secure boot capability and mechanisms for isolated and secure execution environments. Customers can then add their own root of trust and crypto technologies.

The slide also shows a generic block diagram for all the first-gen Catapult variants, which shows support for the Vector extension supporting AI acceleration, as well as basics like FPU, MMU/MPU, and various caches. ECC memory is available for both the L1 and TCM caches.

The video posted below suggests that the automotive cores may include variants of the MCU cores in addition to the 64-bit application processor. The Catapult automotive cores will comply with ISO 26262 automotive standards and will be available “in a range of CPU solutions for each Automotive Safety Integrity Level (ASIL),” says Imagination. Renesas offered a testimonial quote on the automotive core, which suggests the Japanese chipmaker may already be a customer.

 
Catapult Linux support

Catapult CPUs “offer full hardware, software and debug support for SoCs using Imagination IP – complementing its market-leading GPU, AI and Ethernet Packet Processor (EPP) cores,” says Imagination. The cores are compatible with the gem5 simulator.

The platform supports build and debug tools such as GCC, LLVM and GDB, as well as optimized C libraries. Catapult comes with Imagination’s Catapult Studio IDE, which is based on Visual Studio Code. A Catapult SDK will be available for Windows, Ubuntu, CentOS, and MacOS. The SDK includes FreeRTOS and full support for Linux, including reference bootloaders, kernels, and Yocto-based filesystems.

This is not Imagination’s first foray into CPUs or open hardware. The company acquired MIPS Technologies in 2013 for $100 million, and announced a 64-bit Warrior line of MIPS processor IP the following year. The company began to open up the proprietary MIPS architecture in 2015 with the release of a version of its MicroAptiv CPU called MIPSfpga with fully transparent RTL, which was offered free to academic users.

Yet, Imagination, which has long been known for its exceptionally opaque PowerVR GPUs, did not make the final step to convert MIPS into an open architecture. Wave Computing, which acquired the MIPS business, released its first MIPS ISA without license fees or royalties in 2019. The company went bankrupt and remerged as MIPS Technologies, which is working on an 8th Generation of MIPS technology that switches to RISC-V.

AnandTech notes that Imagination has retained some of its MIPS engineers, as well as staff left over from its earlier experiment with its Meta MCU technology. It also retains some patents related to those efforts.

The story suggests that Imagination’s patent holdings and UK location could help boost its prospects from vendors in China and other countries that are wary of getting intertwined with US chipmakers. This advantage would likely increase if Nvidia acquires Imagination’s UK-based GPU rival Arm, although that is looking iffier after the US Federal Trade Commission filed suit against the acquisition.




Catapult overview

 
Further information

The 32-bit microcontroller Catapult design is already in use and the real-time core is available for licensing. The two 64-bit Catapult cores will be available in 2022. An NDA is required to find out more. Meanwhile, a bit more information on Catapult may be found in Imagination’s announcement and Catapult product page.
 

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