Xilinx announced ultra-rugged mil-aero (XQ) and space (XQR) versions of its Arm/Linux-driven, 7nm Versal ACAP SoCs, as well as a Kria Robotics Stack and Vitis Video Analytics SDK for its Zynq UltraScale+ customers.

Xilinx, which is soon to be acquired by AMD, has kicked off its virtual Xilinx Adapt 2021 conference with some announcements regarding its Versal ACAP processor family, among other technologies. The news follows the FPGA-focused chipmaker’s July announcement of its Versal ACAP HBM Series (high bandwidth memory) variation on its Versal ACAP Prime and Premium series, which similarly target datacenter and networking applications. Versal ACAP HBM incorporates HBM2e DRAM, “providing 820GB/s of throughput and 32GB of capacity for 8x more memory bandwidth and 63% lower power than DDR5 implementations,” says Xilinx.

The newly announced, defense grade “XQ” Versal parts are ruggedized for aerospace and defense applications. XQ branded Versal Prime and Premium SoCs, as well as XQ AI Core and XQ AI Edge versions of the embedded, AI-enabled Versal AI Edge and AI Core processors will begin shipping in Q1 2022. The XQ variants will comply with Mil-Std-883 Group D standards and offer “tin-lead (Sn/Pb) content with full mitigation of tin-whiskering.” M-temp (-55 to 125°C) support will be optional.

The space-grade “XQR” Versal ACAP models will be available only for Versal AI Edge and AI Core SoCs starting in late Q2 2022. The XQR processors offer “ruggedized, organic ball grid array packaging with extended qualification and burn-in supporting Mil-Std-883 Class B-grade flow and full radiation tolerance,” says Xilinx. The XQR chips build on technology used on last year’s radiation tolerant RT Kintex UltraScale FPGA family, including the initial XQRKU060 part.

Versal AI Edge simplified (left) and detailed block diagrams
(click images to enlarge)

Like all the 7nm, headless Versal ACAP processors, the XQ and XQR models run Linux on dual 1.76GHz Cortex-A72 cores, which are accompanied by dual 750MHz Cortex-R5F cores. They all offer varying amounts of flexible, FPGA-like “Adaptible Engines,” which on the embedded/edge AI focused Versal AI Edge can achieve up to 520K LUTS performance.

Like the earlier Versal AI Core parts, which target higher-end 5G infrastructure, automotive, and datacenter applications, Versal AI Edge provides “Intelligent Engines” — a tiled array of VLIW and SIMD processing elements that include DSP blocks and NPU-like AI Engine and AI Engine-ML cores. Versal AI Edge enables AI Engine-ML core performance up to 479 TOPS.

 
Kria Robotics Stack and Vitis Video Analytics SDK

In April, Xilinx launched a Linux-powered Kria K26 SOM compute module built around its earlier Arm/FPGA hybrid Zynq UltraScale+ MPSoC, as well as a Kria KV260 Vision AI development board for the module. The chipmaker has now announced a Kria Robotics Stack (KRS) for both.

Kria K26 SOM (left) and Kria KV260 Vision AI Starter Kit
(click images to enlarge)

KRS provides integrated utilities to speed up ROS 2 and Gazebo to “empower faster, secure, and more complete robot behavior,” says Xilinx. KRS will offer an expanding set of reference designs, with plans for KRS application availability via the Xilinx App Store. “KRS helps leverage hardware acceleration into Xilinx devices with high-performance and low latency, in a similar fashion to how Vitis AI helps AI developers implement machine learning inference models into Xilinx devices,” says the company.

The Vitis AI stack, which supports Zynq, Zynq UltraScale+, and Versal, is based on Vitis, which is billed as an easier alternative to the Vivado Design Suite. Xilinx has now announced a Vitis Video Analytics SDK (VVAS) that builds on Vitis AI. VVAS is an “end-to-end” and “edge-to-cloud” video analytics solution equipped with video decoding, pre-processing, AI inference, tracking, and post-processing acceleration features.

The VVAS SDK supports AI models such as YOLO, SSD, ResNet, Inception, RefindDet, ReID, FPN and OpenPose for real-time objection detection, classification, and segmentation. Applications include vehicle and pedestrian traffic pattern analytics, health and safety monitoring, self-checkout and retail analytics, and detecting component defects at manufacturing facilities. A framework allows developers to build applications with plug-ins, software acceleration libraries, and an interface for developing a custom acceleration library to control a custom hardware accelerator.

Architecture diagrams for Vitis AI (left) and Vitis Video Analytics SDK
(click images to enlarge)

In other announcements, Xilinx has expanded Vitis to include libraries for ultra-fast imaging that are optimized and targeted for Versal AI engines. In addition, there are additions to the video and imaging IP portfolio for UltraScale+ and Versal, including 8K scaler and mixer IPs for enabling higher-quality 8K video capture and 8K display with HDMI 2.1 and DisplayPort 1.4.

Finally, Xilinx says that its Zynq RFSoC DFE variant of the UltraScale+, which was originally announced as the Zynq UltraScale+ RFSoC, is now in full production. The Linux-powered SoC provides hardened digital front-end (DFE) application-specific blocks for 5G NR performance and power savings. The Zynq RFSoC DFE also offers programmable adaptive logic “to enable a futureproof solution for evolving 5G 3GPP standards and O-RAN radio architectures,” says Xilinx.

 
Adaptive Computing Challenge

We saw some of these Xilinx announcements on Hackster.io, which is collaborating with Xilinx on an Adaptive Computing Challenge for Vivado ML, Vitis, and Vitis AI development. The contest will award up to $10,000 in three categories: edge computing, data center AI, and big data analytics. There are also special $2,500 challenges for university students and women. The Edge Computing project requires the previously mentioned Kria KV260 Vision AI Starter Kit.

 
Further information

More on the Xilinx announcements may be found in the VVAS and IP software press release and the main announcement with news on the XQ, XQR, Kria Robotics Stack, and more.