Imagination is releasing a free version of its Linux-ready MIPS MicroAptiv CPU to universities called “MIPSfpga,” which will offer fully transparent RTL.

Imagination Technologies has developed a Linux-ready academic version of its 32-bit MIPS architecture MicroAptiv processor design, and is giving it away free to universities for use in computer research and education. As the MIPSfpga name suggests, the production-quality RTL (register transfer level) design abstraction is intended to run on industry standard FPGAs.

Although MIPSfpga is available as a fully visible RTL design, MIPSfpga is not fully open source, according to the announcement from Robert Owen, the Manager of Imagination’s University Programme. Academic users can use and modify MIPSfpga as they wish, but cannot build it into silicon. “If you modify it, you must talk to us first if you wish to patent the changes,” writes Owen.

MIPSfpga architecture
(click image to enlarge)

Like the MCU-like MicroAptiv, MIPSfpga appears to be best suited for running a real-time operating system (RTOS). However, it also similarly includes a memory management unit (MMU) and cache controller that lets it run Linux.

The Linux support is not yet fully developed on the initial run of MIPSfpga packages that will be released to students at Harvey Mudd College on May 13. “There are still some extra IP blocks to be configured for the FPGA and software drivers that need to be written, but we are working on it,” explains Owen.

The MicroAptiv design is used in Microchip’s PIC32MZ MCU, and it will soon appear in the Ineda Systems Dhanush Wearable Processing Unit, some of which support Linux.

MIPS may significantly trail x86 and ARM in the application processor world, but it’s widely used in academia for teaching microarchitecture fundamentals. According to Owen, this is because of all the mainstream processors, it’s the closest to a classic “true RISC” architecture.

x86 “has metamorphosed many times and has become quite complex for university students to understand,” writes Owens. “You could pick ARM, but that’s also become increasingly complex, and was arguably never true RISC in the first place. It’s also fraught with difficulties because the internal architecture is a fiercely guarded secret.”

By comparison, MIPS, which was developed in the ’80s at Stanford by RISC creator John L. Hennessy and others, has always been a relatively open architecture. Hennessy and David Patterson of UC Berkeley published the nitty gritty details in “Computer Architecture: A Quantitative Approach.”

Owens notes that due to this detailed documentation, many MIPS-like and MIPS-compatible chips have prospered over the years. Like fully-licensed, 64-bit MIPS SoCs from companies like Cavium and Broadcom, they are typically focused on Linux.

Creator CI20

China-based Ingenic Semiconductor, for example, has been building MIPS-derived Xburst cores for years, but didn’t formally license the MIPS design and start paying fees to MIPS Technologies until 2011. Imagination’s Linux- and Android-friendly Creator CI20 hacker SBC features a dual MIPS core Ingenic JZ4780 SoC.

 
Inside MIPSfpga

In order to be useful to academics, MIPSfpga enables students “to see the actual RTL, study the inner workings of this RISC processor and run/debug Linux (or other operating systems) on an FPGA,” explained Imagination’s Alexandru Voica in an email. Compared to MicroAptiv, it’s also been simplified, pre-configured, and pre-validated in order to make it easier to work with.

The MIPSfpga configuration was largely designed by of Prof. David Harris of Harvey Mudd College, with Prof. Sarah Harris of the University of Nevada, Las Vegas, preparing the educational materials, writes Owen. The two computer researchers, who are not related, wrote a book called “Digital Design and Computer Architecture,” that helped inspire Owen to pursue the MIPSfpga project.

MIPSfpga introduces some modifications to the MIPS load/store architecture intended to make it more “elegant.” The IP design includes an “instruction bonding” technology that “enables two consecutive loads/stores of the same type which access contiguous memory locations to be fused together by the instruction issue unit,” writes Owen. Instruction bonding can be performed for multiple load/store instructions defined in the MIPS ISA, and can double the performance of memory-intensive operations, he claims.

Other “elegant” MIPSfpga attributes include:

• Shadow registers for fast context switching
• More general purpose registers (32x GPRs)
• More efficient memory addressing and more compact code size (more single operation instructions)
• Less speculative execution (more efficient branching)

The MIPSfpga package includes a detailed guide that helps to ensure that the CPU is running properly on the FPGA, and that it can be programmed and debugged. The guide provides examples for the Terasic DE2-115 (Altera FPGA) platform and the Digilent Nexys4 DDR (Xilinx FPGA) platforms. In the coming months, Imagination will provide the MIPSfpga Fundamentals teaching materials developed by Sarah Harris, to be followed by a MIPSfpga Advanced curriculum.

 
Slowly opening up MIPS

Imagination Technologies acquired MIPS Technologies in 2013 for $100 million, and announced a new 64-bit Warrior line of processor IP that has yet to appear in a production SoC. The company is actively courting Android SoC vendors, as did MIPS Technologies in years past, but has so far met with little success.

Imagination is also reaching out to the embedded Linux and Android development community with the community-backed Creator CI20 board, and is tightening bonds with its licensees with and other new partners with its non-profit, somewhat Linaro-like Prpl organization. Under the Prpl umbrella, Qualcomm is developing a carrier-grade version of the lightweight, low-power OpenWRT Linux distribution, which is often paired with its increasingly popular MIPS-based Atheros WiFi chip for IoT devices.

While Imagination continues to make MIPS more open and attractive to ARM hackers, the chip IP designer’s highly rated PowerVR graphics processing chips have a reputation for being some of the least transparent GPUs on the market. Making PowerVR a bit more visible to developers would likely encourage more ARM developers to jump to MIPS as well.

 
Open source lowRISC SoC gets preview release

While Imagination may well peel back more layers of MIPS for developers, it’s not likely that MIPS or any other mainstream processor architecture will be fully open sourced in the foreseeable future. However, a group called lowRISC is intending to do precisely that.

The lowRISC group plans to release a completely open source, Linux-friendly RISC eco-system, including the ISA, processor silicon, and development boards. On April 13, lowRISC released the first lowRISC preview, which demonstrates support for tagged memory.

RISC-V logo

The lowRISC platform will be based on an emerging open source instruction set architecture (ISA) called RISC V, which will be aimed initially at Linux-based IoT devices. RISC-V is being developed at UC Berkeley by RISC pioneer and aforementioned Hennessy writing partner James Patterson, along with Krste Asanović.

Future lowRISC work will include improved ISA support, collecting performance numbers across a range of tagged memory uses, and tuning the tag cache, says the project. The developers are also working on creating an “untethered” version of the SoC design “with the necessary peripherals integrated for standalone operation.”

 
Further information

Universities can now apply for access to the free Imagination Technologies MIPSfpga design at the Imagination University Programme site. More information may be found in Robert Owen’s MIPSfpga blog announcement.