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Two 64-bit RISC-V cores debut: StarFive Dubhe and CAS Nanhu

Dec 8, 2021 — by Eric Brown 419 views

StarFive has launched its 64-bit RISC-V “Dubhe” core with up to 2GHz @ 12nm performance plus Vector and Hypervisor extensions. Meanwhile, the Chinese Academy of Sciences announced a similarly Linux-friendly, 14nm RISC-V RV64GC “XiangShan Nanhu” core that also clocks to 2GHz.

Chinese RISC-V chipmaker StarFive, which recently showed off a VisionFive V1 SBC with a StarFive JH7100 SoC with dual Cortex-A55 like SiFive U74 cores, has announced the “delivery” of its own RISC-V core called Dubhe. In other China-related RISC-V news, the Chinese Academy of Sciences revealed a line of open source XiangShan RISC-V cores that run Linux, including a new, high performance XiangShan Nanhu design (see farther below).

Highly simplified Dubhe (left) and more detailed XiangShan architectures
(click images to enlarge)

A July report from Intralink on the previous RISC-V Summit held in China said that the Dubhe and XiangShan RISC-V cores were the biggest stories at the conference. The other major Chinese player in 64-bit, Linux-ready RISC-V cores is Alibaba’s T-Head unit, which offers Linux-ready XuanTie cores. These include the recent XuanTie C910, which appeared recently on a dual-core, 1.2GHz XuanTie C910 ICE SoC. The XuanTie C910 cores are variants of the core that formed the basis for the up to 16-core, 2.5GHz XuanTie 910 RISC-V SoC proof-of-concept unveiled in 2019.

StarFive Dubhe


The StarFive Dubhe is a 64-bit RV64GCBVH core with a superscalar design with deep out of order execution. Dubhe is “highly optimized for performance,” says StarFive.

Dubhe can achieve a 2GHz frequency using a TSMC 12nm process. Benchmark specs include SPECint2006 of 8.9/GHz, Dhrystone of 6.6 DMIPS/MHz, and CoreMark of 7.6/MHz. (Back on Mar. 1, a RISC-V blog announcement said that Dubhe had a SPECint2006 benchmark “estimated” to be 31.2 at 3.5GHz and a Dhrystone benchmark is 5.6DMIPS/MHz.)

VisionFive V1

Applications include data center, mobile device, networking, and machine learning. We saw no mention of Linux, but that appears to be a given.

This is StarFive’s first homegrown RISC-V core. SiFive is a distributor and customer of SiFive, and all the other cores listed on its website are SiFive designs such as the U74 cores used on the StarFive JH7100 SoC that powers StarFive’s VisionFive V1 SBC.

The “BVH” extensions at the end of its RISC-V RV64GCBVH designation refer to Bit Manipulation, as well as support for the AI-focused Vector extension and the recently ratified Hypervisor spec for virtualization. The Hypervisor extension is supported on SiFive’s new, Cortex-A77 like SiFive Performance P650 core.

The Dubhe core offers memory coherency support plus floating point, fixed point, and integer data types. Other features include 128 to 1024-bit VLEN, an ALU and data path width of 128 or 256 bits, and full vector register grouping.

Presumably, StarFive will roll its Dubhe into a SoC of its own. Stay tuned.

XiangShan Nanhu

In a RISC-V Summit presentation on Monday, Professor Yungang Bao of the Chinese Academy of Sciences’ Institute of Computing Technology (ICT) showcased his group’s Linux-ready XiangShan cores. He started by detailing the first-generation XiangShan Yanqihu, which appeared in a 28nm tape-out in July.

The XiangShan Yanqihu is an RV64GC compliant, 11-stage, superscalar out-of-order core that can run at up to 5.3 CoreMark/MHz at 1.3GHz with 5W consumption. By comparison, Imagination’s first-gen Catapult RISC-V CPU cores announced this week have a simpler in-order chip design.

The newly announced, second-gen XiangShan Nanhu will achieve tape-out in early 2022. The similarly open source core is based closely on Yanqihu. In fact, CAS/ICT supplies a single architecture diagram for both models (see image at top). The core can be deployed in up to dual-core 14nm silicon and runs much faster than Yanqihu at about SPEC06 20 marks @ 2GHz.

XiangShan Nanhu performance specs (left) and L2/L3 cache overview, presented by ICT’s Yungang Bao at this week’s RISC-V Summit
(click images to enlarge)

The Nanhu has a new front-end design with decoupled branch prediction and instruction fetch for higher accuracy and batch throughput, said Bao. There are also improvements to the backend, including a better scheduler, and new I/O support for PCIe and USB. The core’s new “high frequency, high performance” L2/L3 design was “inspired” by SiFive’s block inclusive cache, and Bao thanked SiFive for the technology in his presentation.

Next year, CAS plans to announce a new XiangShan design with the RISC-V Vector extension for applications such as AI acceleration. In response to a question, Bao said CAS would like to see a “Red Hat” type company pick up the XiangShan cores for commercialization. The Red Hat allusion appears to suggest ICT is looking for a company that is centered around selling services for an open source product.

CAS is backed by the Chinese government. Other government-backed RISC-V initiatives include the EU’s European Processor Initiative, which is working on a Linux-ready EPAC core.

Further information

The StarFive Dubhe core is available for licensing. More information may be found in StarFive’s brief announcement in publications such as EETimes, as well as the Dubhe product page.

CAS ICT’s first-gen XiangShan Yanqihu core is freely available, and the Nanhu model will be available in early 2022. More information may be found on the XiangShan GitHub page and on the RISC-V Summit presentation (fast forward to 10:23 mark — the discussion of Nanhu starts at 25:40).

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