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TI spices up Jacinto auto SoCs with ADAS support

Oct 22, 2014 — by Eric Brown 2,130 views

TI is prepping two OMAP5 based Linux-and Android-ready automotive SoCs with extra DSPs and imaging GPUs, to handle digital clusters, ADAS, and infotainment.

Texas Instruments never misses an opportunity to prove that its digital signal processor (DSP) chips are still relevant in the modern age. The latest role for TI’s DSPs is in its Linux- and Android-ready “Jacinto 6” automotive system-on-chip, which already incorporates one DSP. Now, the chipmaker has announced two new versions of the Jacinto, dubbed “DRA75x,” to differentiate them from the existing DRA74x Jacinto 6 and stripped-down DRA72x Jacinto 6 Eco.

The two new models add two DSPs in order to generate graphics for instrumentation clusters. They can also fulfill their existing role of running an in-vehicle infotainment (IVI) display, and without any performance loss, says TI.

Jacinto 6 Ex block diagram
(click image to enlarge)

Both the Jacinto 6 EP and Jacinto 6 Ex offer dual 1.4GHz DSPs, as well as all the existing Jacinto components. The Ex model also adds a pair of vision coprocessors to generate more advanced augmented reality displays for digital cockpits, also known as instrumentation clusters. It also enables “informational” advanced driver assistance systems (ADAS) features, such as 360-degree park assist, augmented reality head-up displays, and driver monitoring and identification.

Digital cockpit UI generated by the Jacinto DRA75x SoCs

The Jacinto 6, which ships with Linux, Android, and QNX SDKs, has been a popular choice among next-generation GENIVI and Automotive Grade Linux (AGL) based designs. It’s running on GlobalLogic’s AGL-based Nautilus in-vehicle infotainment (IVI) and telematics platform, which currently uses Android and will soon offer Tizen Linux, as well.


Derived from TI’s OMAP5 design, the Jacinto 6 combines two Cortex-A15 cores with four Cortex-M4 cores, as well as a TMS320C66x VLIW floating-point DSP for software-defined radio (SDR), and audio and speech-processing. In addition, the Jacinto 6 features a pair of Imagination Technologies SGX544 3D GPUs, as well as Vivante’s 2D GC320 GPU, and other coprocessors.

DSP partitioning on Jacinto 6 Ex
(click image to enlarge)

The second, 1.4GHz, TMS320C66x DSP on the Jacinto 6 EP and Ex offers 22 GFLOPS and 60 GMACS performance, says TI. The DSP supports image manipulation tasks such as dynamically stitching multiple cameras into a single, surround, or overhead view, says the company. The second DSP is also said to enable augmented radio configurations, such as multi-tuner, multi-modal configurations leveraging antenna diversity and background scanning.

In addition, the DSP supports enhanced audio and speech processing, active noise control (ANC), voice recognition, and other technologies. The second DSP enables concurrent radio/audio signal processing and image manipulation processing, “with headroom to spare.” The Jacinto 6 EP is said to lower BOM cost by incorporating additional USB, video input, and PCIe interfaces.

External links from Jacinto 6 Ex (left), and Jacinto 6 product overview
(click images to enlarge)

The higher end Jacinto 6 Ex enables “fusion between IVI and informational ADAS,” says TI. In addition to offering the second DSP, it provides two embedded vision engines (EVEs) for enabling simultaneous informational ADAS and infotainment functionalities “without compromising the performance of either system,” says the chipmaker. Each EVE chip is comprised of an optimized vector coprocessor and a 32-bit programmable RISC core, which together offload fixed-point array processing tasks.

The EVE chips are said to run “simultaneous ADAS algorithms faster, and with greater power-efficiency than ever before.” Potential applications include object and pedestrian detection, augmented reality navigation, and driver identification. The chips make use of cameras both inside and outside the car “to enhance the driving experience without actively controlling the vehicle,” says TI. These ADAS apps are typically presented via the center stack, the programmable cluster, and/or a head-up display.

Pin compatibility with Jacinto 6

Both SoCs are software and pin-to-pin compatible with existing Jacinto 6 SoCs. In addition to the Jacinto 6 features noted farther above, the new SoCs also share the ability to support up to four 1080p displays and four 1080p video and camera inputs. Cameras and HD displays can be connected to the Jacinto via FPD-Link III Ser/Des chipsets, says TI.

Other common features of the four Jacinto 6 SoCs include DS90UH925Q serializer and DS90UH926Q deserializer chips to carry digital video, audio, and bidirectional I2C control signals concurrently over a single twisted pair cable. Meanwhile, separate DS90UB913AQ serializer and DS90UB914AQ deserializer chips connect camera modules via coax.

The Jacinto 6 also integrates TI’s TPS659039-Q1 power management IC, which supports harsh automotive requirements, and offers AEC-Q100 qualification. The SoC is also designed to work with TI’s WiLink 8Q wireless chip, which includes WiFi, Bluetooth, and GNSS.

Further information

The DRA75x Jacinto 6 EP and Jacinto 6 Ex processors are currently sampling, and are scheduled for production before the end of the year. More information may be found at TI’s DRA75x product page.

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