[Updated: July 24] — SiFive has upgraded its RISC-V Core IP, including its Linux-enabled U5- and U7-series CPUs, with a “20G1” release that boosts performance and reduces power. Meanwhile, Codasip unveiled a Linux-ready “Bk7” RISC-V core.

RISC-V industry leader SiFive had updated is RISC-V designs for higher performance, lower power consumption, and reduced size with a Core IP 20G1 release available with the latest version of its SiFive Core Designer platform. Improvements have been made to the U-, S-, and E-series cores from level 2 to 7, including the Linux-ready U3-, U5, and U7-series. In other RISC-V news, Codasip released IP for a 64-bit, 7-stage Bk7 core that can run Linux (see farther below).

Core IP 20G1 improvements to the 64-bit U7-series, such as the Cortex-A55 like U74 and quad-core U74-MC, are said to include reduced power consumption by more than 25 percent. The IP also increases load bandwidth up to 2.8x for streaming data applications such as AI acceleration, claims SiFive. It is unclear to what extent non-AI applications might be accelerated.

SiFive does not list performance specs for the other CPU core series, such as the Linux-ready U54 cores found on SiFive’s HiFive Unleashed SBC and Microchip’s FPGA-enabled PolarFire SoC. Yet, SiFive informed us that: “We highlighted the U74 changes as best case, and other standard cores see similar improvements.”

Core IP 20G1 improvements vs. earlier 19.08 release (left) and U74-MC block diagram
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The Core IP 20G1 release is an update to existing IP rather than a new architecture like the U7-series or the subsequent, Cortex-A72 like U8-Series, which was announced last October and is not part of the 20G1 revamp. In addition to the U7 improvements, the E3- and Cortex-M7-like E7-Series designs now offer a RISC-V Embedded RV32E extension, enabling a reduced area of up to 11 percent. The cores have also been refreshed with enhanced real-time capabilities and they offer more comprehensive support for FreeRTOS.

SiFive has added Xilinx’s UltraScale+ based, FPGA-enabled VCU118 Evaluation Kit as a supported development platform for its RISC-V designs, including multi-core designs. In addition, the Core IP 20G1 release improves SiFive’s Secure Shield software, including new support for the SiFive Shield Hardware Cryptographic Accelerator (HCA) IP add-on option.

Xilinx VCU118
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SiFive notes that the SiFive Core Designer with the Core IP 20G1 release includes its SiFive Insight portfolio of trace and debug IP, software, and tools. SiFive Insight supports integration with Arm Coresight to ease development of heterogenous Arm/RISC-V SoC designs.

Earlier this year, SiFive and CEVA announced that CEVA-BX audio DSPs, CEVA-XM vision chips, and up to 12.5-TOPS NeuPro AI processors were being added to SiFive’s DesignShare program, enabling customers to create custom “Edge AI SoCs” built around SiFive’s RISC-V CPUs. DesignShare allows customers to use proprietary IP available from participating chipmaking customers of SiFive’s RISC-V CPUs. In brief, SiFive can help quickly negotiate the licensing of various coprocessor IP without requiring upfront payments.

 
Codasip’s 64-bit Bk7 runs Linux

Codasip has released its first RISC-V CPU IP that can run Linux. The 64-bit Bk7 core offers a single in-order, 7-stage pipeline compliant with the RV64IMAFDC ISA. The design joins other Codasip RISC-V IP including the 3-stage pipeline Bk3 and the 5-stage pipeline Bk5 and Bk5-64.

Codasip Bk7 pipeline
(click image to enlarge)

The Bk7 design incudes a memory management unit (MMU) and support for privilege modes and RISC-V atomic and floating-point extensions. Other features include an internal interrupt controller, dynamic branch prediction, JTAG and RISC-V debug, and standard bus interfaces including AMBA.

The Bk7 is touted for its easy customizability, both due to the open RISC-V architecture and the company’s Codasip Studio toolset. Codasip Studio provides a high-level core description written in a C-like language called CodAL that enables easy customization. Studio then uses the updated description to “automatically generate a complete customized HDK and SDK, including a full UVM verification environment,” says Codasip.

With the Bk7, Studio has been updated with a new, module-based architecture that enables easier CodAL editing, says the company. Other bundled software includes RTL code, CodeSpace IDE, C compiler, source files, a compilation guide for Linux, and a Linux boot demo SoC.

Customizable options include store buffer and the branch predictor, instruction and data caches, among others. Future Bk7 releases will add tightly coupled memories, dual issue microarchitecture, and multicore support, says Codasip.

Other recent Linux-ready RISC-V core and SoC designs include Andes’ AndesCore 27-series IP and Alibaba’s 16-core XuanTie 910 SoC design. Both designs include AI acceleration, which is also found on the lower-end RISC-V Kendryte K210 processor used on products such as the Sipeed MaixCube dev kit. The MCU-like K210 nominally supports the stripped-down uCLinux but is better suited to FreeRTOS.

RISC-V continues to see increased adoption, thanks in part to improvements to verification and validation processes. For a cheekier, birds-eye view of the RISC-V scene you can check out this recent analysis from The Register, which points out that for most chipmakers, RISC-V’s attraction has less to do avoiding paying licensing fees as it does with the open source platform’s ease of customization.

 
Further information

The SiFive Core IP 20G1 release is available now with SiFive Core Designer. More information may be found in SiFive’s announcement and this more detailed blog post. There is also an upcoming webinar on the release to be held Aug. 6.

Codasip’s Bk7 IP design is now available for licensing. More information may be found in the Bk7 announcement.