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SiFive adds mid-range Essential 6-Series RISC-V cores, including two Linux-ready models

Dec 8, 2021 — by Eric Brown 1,414 views

SiFive announced a “21G3” release of its RISC-V cores, including a new, embedded focused “Essential 6-Series” featuring the Linux-ready, 64-bit U64 and a similar U64-MC designed for quad-core SoCs.

Leading RISC-V core and SoC vendor SiFive, which last week unveiled a Cortex-A77 like SiFive Performance P650 core for up to 16-core SoCs, has released a 21G3 update to its entire product line. SiFive also announced a new mid-range line of 64-bit and 32-bit Essential 6-Series core IP, including Linux-friendly, 64-bit U64 and U64-MC models.

The Essential 6-Series slots in above the Essential 5-series, SiFive’s new name for its the processors that include the U5-series/U54 cores found on the FU540 SoC that powers SiFive’s HiFive Unleashed SBC. The cores are less powerful than the Essential-7 cores, which include the Cortex-A55 like U74-MC, which runs Linux on the HiFive Unmatched SBC. The series also includes the MCU-like S6 and E6.

Block diagram for Essential 6-Series U6 core complex, which powers the U64 and U64-MC
(click image to enlarge)

SiFive changed to the Essential branding for its low and mid-range cores when it released its 21G2 update in July. Whereas that update featured an 11 percent speed boost on its Essential 7 cores, among other enhancements, the 21G3 release introduces improved clock gating and power management across the entire SiFive portfolio and adds SiFive Shield WorldGuard support to the Essential family. Shield WorldGuard was announced as a feature of the high-end P650.


SiFive also announced that SiFive Intelligence Extensions, the RISC-V Vector (RVV) extension based enhancement for AI found on the U7-based SiFive Intelligence X280, now supports BFLOAT16 compute, quantization acceleration, and improved multi-cluster support. SiFive also says that the entire SiFive Performance family now features the new RISC-V Hypervisor extension for virtualization, which means that the SiFive Performance P550 now supports it in addition to the P650.

Essential 6-Series

The single-core Essential 6-Series U64 core is “ideal for applications requiring high-throughput, single-thread performance in a power-constrained environment,” says SiFive. Applications include Linux-driven general purpose embedded, industrial, IoT, high-performance real-time embedded, and automotive.

The U64 is listed with 2.07 DMIPS/MHz and 3.73 CoreMark/MHz benchmark scores. In July, SiFive said that the newly accelerated, Essential-7 U74 cores tested at 5.7 CoreMark/MHz and 3.2 Dhrystone/MHz.

The U64 integrates 32KB each of L1 I-cache and L1 D-cache, as well as 128KB of L2, all with ECC support. The L2 cache “can be configured into high speed deterministic SRAMs” for real-time tasks, says SiFive.

The U64 provides 8-region physical memory protection and virtual memory support with up to 37 physical address bits. Other features include CLINT and PLIC.

The U64-MC is similar to the U64 but is designed for up to quad-core SoCs. The design also includes a 64-bit S61 monitor core, which enables hard real-time determinism. Applications are same as with the U64 but aimed at higher-end scenarios that require high-throughput performance with real-time guarantees.

The new, 32-bit S61 core found on the U64-MC design is similarly available in a quad-core focused variant: the S61-MC. The S61 is a high-end MCU aimed at latency-sensitive applications in domains such as storage and networking. It has a 16KB, 2-way instruction cache and supports up to 64KB of Data Tightly Integrated Memory (DTIM). SiFive also launched lower-end E76 and E76-MC MCU cores as part of the Essential 6-Series.

Like all the SiFive cores, the Essential 6-Series is touted for its high performance per square millimeter. At a press briefing earlier this week at the RISC-V Summit called “RISC-V: The Past, Present, and Future of RISC-V,” SiFive CTO Yunsup Lee, noted that the size advantage is due in large part to RISC-V supporting compressed instructions. He said that the new Armv9 architecture eliminates compressed instructions, which “was a really bad choice.” With RISC-V, on the other hand, “we can have more instructions in the size, resulting in smaller processors,” said Lee.

Further information

The 21G3 release is available now to SiFive customers. No pricing or availability information was provided for the Essential 6-Series. More information may be found in SiFive’s announcement, which we saw on AIThority, as well as the newly updated Essential product page.

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