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RISC-V news from T-Head Semiconductor and SiFive

Nov 6, 2022 — by Giorgio Mendoza 3,740 views

Last week T-Head semiconductors announced their XuanTie C908 which implements a 9-stage pipeline along with an AI acceleration engine for AR/VR apps. Similarly, SiFive also shared details about their new P670/P470 RISC-V processors for wearables and smart consumer devices.

T-Head Semiconductor mentioned that the XuanTie C908 is offered in two architectures: RV32GCB[V] (32-bit) and RV64GCB[V] (64-bit). Moreover, the C908’s performance vs cost is in between the C910 and the C906 processors. The company expects the C908 to target image and video processing applications. 


 XuanTie C908 architecture
(click image to enlarge)

According to the announcement, the XuanTie C908 is based on the TSMC’s 12nm process and it can run at a frequency of up to 2.0GHz. Also, its dynamic power consumption was estimated to be 52.8 mW/GHz per core. 

  • XuanTie C908:
    • RISC-V Bit manipulation 1.0 instruction extension including the carry-less multiplication (zbc)
    • Supports the RV32 COMPAT mode (merged into Linux mainline version 5.19)
    • Optional VPU compatible with RISC-V Vector 1.0 instruction set extension
    • IEEE-754 compatible half-precision, and other floating-point operations, i.e. BF16 operations
    • Adopts the Sv39/Sv48 virtual address system and holds up Svnapot and Svpbmt

      C906 vs C908 benchmarks
(click images to enlarge)

The company also mentioned, “XuanTie C908 uses a two-level cache system to support hardware cache coherency and optional ECC. In this multi-cluster architecture, each cluster can contain 1 to 4 cores. The bus interface supports AXI4/ACE protocol with two optional interfaces: a Device Coherence Port (DCP) and a Low Latency Port (LLP). DCP maintains data coherency with external I/O masters, while the LLP access peripherals.  The XuanTie C908 provides the enhanced physical memory protection (ePMP) unit that allows a maximum of 64 regions. The C908 also backs up for RISC-V Debug and Platform-Level Interrupt Controller (PLIC) which can be configured up to 1023 interrupt sources.”


      C906 vs C908 AI benchmarks 
(click image to enlarge)

On the other hand, SiFive announced the P670 and the P470 high performance RISC-V processors which offer “a finely-tuned combination of compute-density, power efficiency, and robust feature sets ideal for a wide range of applications and markets.”

Both SiFive processors share the following features: 

  • Support for virtualization, including a separate IOMMU for accelerating virtualized device IO
  • Full, Out-of-Order, RISC-V Vector implementation, based on the ratified RISC-V Vector v1.0 Specification
  • First to market with the RISC-V Vector Cryptography extensions, SiFive World Guard system security
  • Full RISC-V RVA22 profile compliance
  • New, Advanced Interrupt Architecture (AIA) compliant interrupt controller, with better support for Message Signal Interrupts (MSI) and virtualization.
  • Enhanced scalability with fully coherent multi-core, multi-cluster, with support for up to 16 cores

SiFive also specified that both processors achieve a maximum frequency exceeding 3.4GHz in 5nm. However, the P670 has a performance greater than 12 SpecINT2k6/GHz while the P470 offers a performance greater than 8 SpecINT2k6/GHz.

SiFive P670 pipeline (left) and benchmarks (right)
(click images to enlarge)

The P670 also provides a single threaded performance, 2x compute density compared to legacy solutions and it includes a 2x 128-bit Vector ALUs compliant with the ratified RISC-V Vector v1.0 specification. 

Some notable features of the P470 include “4x compute density in comparison to the leading competitor, 1x 128-bit RISC-V Vector ALU compliant with the ratified RISC-V Vector v1.0 specification.” SiFive also mentioned they will release a P450 variant with an area-optimized version without the Vector Unit. 

SiFive P670 pipeline (left) and benchmarks (right)
(click images to enlarge)

Companies such as Qualcomm and Samsung also expressed potential interest in these new SiFive processors.

“We are excited to see RISC-V solutions for wearable and consumer devices becoming a reality, and we are looking at possibilities of integrating SiFive’s latest products into Snapdragon platforms,” said Ziad Asghar, Vice President, Product Management- Snapdragon Technologies and Roadmap at Qualcomm.

“Samsung’s System LSI Business holds a wide portfolio of solutions for various applications, such as mobile, wearables and other consumer devices. We look forward to evaluating how the latest RISC-V innovations from SiFive can enhance our offerings,” said Jinpyo Park, VP of the Innovative AP Development Team, Samsung Electronics System LSI Business.

Further information

The XuanTie C908 announcement can be found in the RISC-V blog using this link. The original SiFive announcement is available in the company’s News section

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