NXP announced a safety-critical “S32G” network processor aimed at ADAS and autonomous cars that runs Linux on a quad -A53 block along with 3x Cortex-M7 cores, network accelerators, and packet forwarding and hardware security engines.

NXP has begun sampling an S32G274A, the first of four S32G gateway processors that are the first of NXP’s MCU-like S32 vehicle networking processors to include Cortex-A processors. Like the newly announced, AI-enabled i.MX8 Plus, the SoC ships with a Linux BSP.

S32G

The S32G is billed as a gateway processor for ADAS and autonomous cars. However, this is not a comprehensive, soup-to-nuts autonomous car platform such as Nvidia’s recently announced Drive AGX Orin, a more powerful follow-on to the automotive version of its AGX Xavier (see farther below). Its more of a gateway hub for any smart car that can also act as an ADAS controller.

When the first i.MX8 SoC — the up to hexa-core -A72 and -A53 i.MX8 QuadMax — was announced back in 2016, it was billed as an automotive processor. Since then, the SoC has morphed into a more general-purpose high-end SoC. With the S32G, NXP has introduced a more automotive-specific Cortex-A SoC that is instead linked to its S32 family of automotive MCUs.

The headless S32G is billed as a gateway processor in that it acts as a smart hub for automotive components controlled by its own trio of Cortex-M7 chips as well as other S32-family MCUs. The SoC can also integrate input from cameras, radars, and ultrasonic and lidar systems, as well as lower-end ICs, ASICs, and sensors to provide a seamless in-vehicle processing network. It can also act as a network hub companion to a separate driverless car computer.

Flexible use scenarios for the S32G in domain and zonal architectures
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The S32G is particularly well suited for what NXP sees as a new wave of service-oriented “domain vehicle” architectures, in which the SoC could act both as the gateway and as a separate ADAS safety controller. It can also act as the central computer or zonal gateway in more traditional zonal vehicle architectures (see diagram above).

The S32G offers ASIL D functional safety support compliant with the D level of Automotive Safety Integrity Level (ASIL) specified under ISO 26262. It’s designed for “securely managing data transmission around the vehicle and protecting safety critical applications from malicious intent,” says NXP.

The S32G offers fail-operational fault recovery features, which enables detection, isolation and resolution of faults without system shutdown. Security features include hardware crypto acceleration and Public Key Infrastructure (PKI) support for trusted key management, enabled by a firewalled Hardware Security Engine (HSE).

S32G conceptual diagram (left) and block diagram
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While handling real-time safety-critical duties with the Cortex-M7 cores and security components, the S32G also has a Linux-driven, quad-core, Cortex-A53 brain capable of handling applications expected for future electric-powered ADAS and autonomous vehicles. These “service oriented” gateway features include usage-based insurance, vehicle health monitoring, and fleet management services.

According to a Forbes analysis of the announcement, the S32G is adept at data reduction. It fuses and analyzes real-time data from sensors for driver assist ADAS input, and then reduces the raw data to the bare minimum that needs to be sent to other in-vehicle computing systems, cloud services, or computers in surrounding vehicles and infrastructure.

In a smart car scenario, GbE processing would consume about 90 percent of the CPU processing, says Forbes. To reduce this, a variety of networking accelerators and a Packet Forwarding Engine (PFE) for Ethernet are integrated to reduce that to approximately 0.2 percent, says the story.

As Forbes describes it there are three “pairs” of Cortex-M7 cores operating in lockstep mode, although the documentation suggest there are only three cores running in lockstep for redundancy. “Each core in the pair is running the same code, providing the ability to detect any anomalies in processing across those pairs, while each pair can be doing different tasks,” says Forbes.

The four Cortex-A53 cores can also be optionally run in lockstep mode so each pair of cores can run tasks simultaneously. This is an “industry first,” says NXP.

Networking accelerators include a Low Latency Communications Engine (LLCE), as well as CAN FD, FlexRay, 4x SPI, and 4x LIN (Local Interconnect Network) accelerators. (LIN is low-cost automotive alternative and supplement to CAN.)

There’s also a Packet Forwarding Engine (PFE) for Ethernet networks that provides stateful firewall, classification, and header manipulation and offload processors. The SoC supports 4x GbE or 2.5GbE ports with Time-Sensitive Networking (TSN), a feature found on the new i.MX8 Plus.

Peripheral support includes SPI, I2C, LIN, CAN FD, FlexRay, USB 2.0 OTG, and PCIe 3.0. There are also watchdog, system, and Flex timers and dual SAR ADC interfaces. A variety of memories are supported including DDR4, and there’s support for -40 to -105°C temperatures.

A Linux BSP will be provided along with AUTOSAR and S32 Design Studio IDE software. The S32G is also supported by the AUTOSAR Adaptive standard. Wind River just announced S32G support with its VxWorks RTOS and its Wind River Helix Virtualization Platform, which also encompasses Wind River Linux.

S32G-VNP-RDB reference design board
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NXP will offer an NXP S32G-VNP-EVB evaluation board — Avnet and Arrow have empty, “request a quote” holding pages here and here. There’s also an S32G-VNP-RDB reference design board (see image above).

NXP announced a TSN-ready SJA1110 automotive Ethernet switch designed for use with the S32G, which it says is the first to have built-in safety features. The switch offers 100BASE-T1 PHYs, hardware-assisted security, and multi-gigabit interfaces. NXP’s VR5510 power management IC is also designed to work with the S32G and the SJA1110.

 
Further information

The S32G274A is sampling now, with more S32G models on the way. No production release date was announced. More information may be found in NXP’s S32G announcement and product page.