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NXP unveils ultra-secure i.MX9 and low-power i.MX8ULP SoCs

Mar 4, 2021 — by Eric Brown — 2015 views

NXP previewed an NPU-enabled “i.MX9” platform and unveiled low-power, Cortex-A35 based i.MX8ULP and Azure Sphere enabled i.MX8ULP-CS SoCs — all with “Energy Flex” power management and “EdgeLock” security.

NXP offered a glimpse into some foundational technologies of an upcoming i.MX9 family of processors, including “EdgeLock” on-die security, RISC-V-based “Energy Flex” power management, and the Arm Ethos U-65 microNPU for AI acceleration. The Netherlands-based chipmaker did not, however, detail the CPU architectures, core counts, performance, GPUs, and other details.

NXP also announced with more details an i.MX8 spin on its Ultra Low Power “crossover” product line. The Linux-driven, 28nm, i.MX8ULP chips include a single- or dual-core, Cortex-A35 based i.MX8ULP and an almost identical, but single-core i.MX8ULP-CS product that adds Microsoft Azure Sphere security technology (see farther below).

 
i.MX9 and its Ethos U-65 microNPU

The i.MX9 processors will use TSMC’s 16/12nm FinFET fabrication process compared to 28nm for the top-of-the-line, hexacore -A72 and -A53 i.MX8 QuadMax and 14nm for the newer, quad-core -A53, 1.8GHz i.MX8M Plus.



Arm Ethos models and their intended applications
Source: NXP
(click image to enlarge)

While the i.MX8M Plus is the only i.MX processor with an NPU for AI acceleration, all the i.MX9 variants will provide an NPU. At least one, if not all the models, will feature the 1-TOPS Arm Ethos U-65 microNPU, which was announced last October. It is likely that some models will offer higher-end NPUs.

Arm’s Ethos U-65 is a follow-on to the 0.5-TOPS Ethos-U55 microNPU, which is designed to work with the new Cortex-M55 MCU. Earlier models include the higher-end Ethos-N77 (4-TOPS), Ethos-N57 (2-TOPS), and Ethos-N37 (1-TOPS) NPUs.

The low-power Ethos-U65 “maintains the MCU-class power efficiency and architectural benefits of the Ethos-U55, while extending its applicability to higher performance Cortex-A-based system-on-chip (SoC)s,” says NXP. The chipmaker was a lead developer with Arm on both microNPUs.

The Ethos-U65 is designed to “accommodate the latency” of the DRAM used on Cortex-A platforms. The NPU supports up to 512GOPS performance when running at 1GHz, and is capable of object recognition in less than 3ms when working with the MobileNet_v2 deep neural network.

Edge AI applications enabled by the Ethos-U65 with i.MX9 are said to include multi-object recognition and spoof-free multi-face recognition in millisecond inference time, voice-based systems that can recognize natural language and accents, and sequence analysis for gesture recognition. The pairing will also support anomaly detection for industrial predictive maintenance and synthetic sensors in smart homes.

The Ethos-U65 is designed to work closely with real-time MCUs, says NXP. This suggests that like all the i.MX8 processors, the i.MX9 will feature Cortex-M or -R cores.

Other likely features, which are found on the i.MX8M Plus might include DSPs, ISPs, and of course CPU and GPU cores. Likely CPU candidates might include Cortex-A55 and perhaps on some models, Cortex-A73 or Cortex-A75 cores, perhaps in combination with Cortex-A55.

 
Energy Flex and EdgeLock

Aside from AI, the other major enhancements are available on both the i.MX9 and the i.MX8ULP series: Energy Flex power management and EdgeLock security. Energy Flex provides “fine-grained power control” and optimized energy efficiency, says NXP. Built around an NXP-made RISC-V PMIC core, the subsystem can govern more than 20 different power mode configurations to as low as 30 microwatts.

On the i.MX8ULP and i.MX8ULP-CS, Energy Flex delivers as much as 75 percent improved energy efficiency, claims NXP, apparently comparing the SoCs to the i.MX7ULP.

On the i.MX9, the technology reduces power via the SoC’s heterogeneous domain processing capability. NXP defines this as “independent applications processor and real-time domains with a separate low-power multi-media domain.”

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Energy Flex offers additional “design techniques and process technology to maximize performance efficiency,” says NXP. For example, low power audio applications can be powered by the real-time domain independently of higher end cores, which can be switched off. The real-time domain is also well-suited to industrial applications such as a CAN network requiring fast boot of less than 100 milliseconds, says the company.

EdgeLock is defined as a “security enclave” and “ground-breaking security IP,” which is baked into the i.MX9 architecture. The on-die technology provides a pre-configured security subsystem with its own dedicated security core, internal ROM, and secure RAM. The technology is said to ease implementation and help designers avoid costly security implementation errors.

EdgeLock features autonomous management of security functions, including silicon root of trust, run-time attestation, trust provisioning, tamper detection, and SoC secure boot enforcement. Other features include fine-grained key management, extensive crypto services, and simplified security certifications. EdgeLock can intelligently track power transitions from user applications to help prevent new attack surfaces from emerging, says NXP.

 
i.MX8ULP and i.MX8ULP-CS

As with the i.MX9, no production schedule was listed for the i.MX8ULP and i.MX8ULP-CS crossover applications processors. However, these power-sipping follow-ons to the Cortex-A7 powered i.MX7ULP appear to be closer to fruition. The i.MX7ULP has yet to really take off, but the Cortex-A9 based i.MX6 UltraLite (UL) and similar i.MX6 ULL have been much more widely adopted for low-power IoT. There is also a headless i.MX6 ULZ model.

Like the earlier UL and ULP SoCs, the Azure Sphere equipped i.MX8ULP-CS is limited to single CPU cores, but the i.MX8ULP is also available with dual cores. Like the i.MX7ULP, the new SoCs are fabricated with a power-efficient, 28nm FD-SOI (Fully-Depleted Silicon-On-Insulator) process, but they advance to a faster, up to 1GHz Cortex-A35 architecture. Cortex-A35 is also used by the up to quad-core i.MX8X, which is currently the most power efficient of the i.MX8 SoCs.

The i.MX8ULP and i.MX8ULP-CS are further equipped with a Cortex-M33 core, 3D and 2D GPUs, and a Cadence Tensilica Hifi 4 DSP, which is also found on the i.MX8M Plus. There is also a “Fusion” DSP for low-power audio/voice and edge AI/ML processing.



i.MX8ULP (left) and i.MX8ULP-CS block diagrams
(click images to enlarge)

The block diagrams show a pair of 32KB I and D caches along with basics such as Arm Neon and TrustZone. There is support for 32-bit LPDDR3, MIPI-DSI and -CSI, and 10/100Mbps Ethernet, among other I/O.

The i.MX8ULP-CS incorporates Microsoft’s Azure Sphere security technology. Aside from that difference and the single CPU core, the CS model appears to differ only in that it has 1x USB 2.0 OTG interface instead of 2x and half the L2 cache with 256KB instead of 512KB.

In July 2019, NXP announced it was working on a Cortex-A35 based i.MX8 SoC that uses the FD-SOI process and incorporates Azure Sphere. The announcement went on to describe major features that fit the profile of the i.MX8ULP-CS.



Azure Sphere interactions on i.MX8ULP-CS
(click image to enlarge)

Azure Sphere, which features a Linux kernel, has appeared on products such as Seeed’s Azure Sphere MT3620 Development Kit and Avnet’s Azure Sphere MT3620 Starter Kit. Both products use the Azure Sphere certified MediaTek MT3620, which combines Cortex-A7, Cortex-M4F, and Microsoft Pluton secure chips.

The Pluton chip is enabled on EdgeLock secure enclave as the secured root of trust built into the silicon itself. The Azure Sphere OS is designed to work with the cloud-based Azure Sphere Security Service. The i.MX8ULP-CS provides “ongoing OS updates and security improvements for over ten years,” says NXP.

 
Further information

No pricing or availability information was provided for the i.MX9, i.MX8ULP, and i.MX8ULP-CS. More information may be found in NXP’s umbrella announcement, as well as an i.MX9 announcement, an i.MX9 product page (with limited details), and a press release for EdgeLock.

There is also an i.MX8ULP/i.MX8ULP-CS announcement and preliminary product pages for the i.MX8ULP and i.MX8ULP-CS.

 

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