Mentor’s “Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit” offers Mentor Embedded Linux, Nucleus, Code Sourcery, a hypervisor, and an Android 6.0 BSP.

Mentor (formerly Mentor Graphics), which is now a Siemens business unit, likes to focus on supporting a few complex multicore SoC families with its embedded development tools, creating a one-stop shop for developers. For example, it offered comprehensive support with its Mentor Embedded Linux for AMD’s embedded G-Series SoCs. This month it has turned its attention to the 64-bit ARM/FPGA hybrid Zynq UltraScale+ MPSoC system-on-chip.

Last year, Mentor Graphics announced basic Android 5.1 and Linux support for the Zynq UltraScale+ MPSoC, and earlier this month, Mentor announced an Android 6.0 BSP for the SoC. This week, it followed up with a comprehensive Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit.

Simplified Zynq UltraScale+ block diagram
(click image to enlarge)

Mentor’s new kit includes optimized versions of the Yocto Project based Mentor Embedded Linux (MEL), as well as Mentor’s Nucleus RTOS, Mentor Embedded Hypervisor, and Code Sourcery tools. The kit also integrates the new Android BSP.

Both MEL and Nucleus can run natively on the Zynq UltraScale+ MPSoC’s Cortex-A53 cores in Asymmetric Multi-Processing (AMP) mode, or across all Cortex-A53 cores in Symmetric Multi-Processing (SMP) mode, says Mentor. MEL and Nucleus can also run as a guest OS on Mentor Embedded Hypervisor, which Mentor defines as a “small-footprint type 1 hypervisor.”

Mentor Embedded Linux architecture
(click image to enlarge)

The kit also includes the Mentor Embedded Multicore Framework (MEMF), which allows developers to configure and deploy multiple OSes across heterogeneous Zynq UltraScale+ MPSoC processors with or without a hypervisor. The framework is said to support “seamless” inter-process communication between MEL, Nucleus RTOS, and bare metal. The framework can be configured with MEL as the master OS, letting it boot and shut-down other MEL instances running on Cortex-A53 cores, as well as Nucleus RTOS or bit manipulation engine (BME)-based applications running on Cortex-A53 or -R5 cores.

The Code Sourcery Sourcery Codebench application provides a single development environment for all MPSoC cores and runtimes based on GCC/G++ tools. CodeBench’s Sourcery Analyzer tool enables developers to create and optimize embedded Linux, RTOS, hypervisor, and bare metal based applications.

The previously announced Android 6.0 (Marshmallow) BSP is built on Android Open Source Project (AOSP), as well as source code and pre-compiled binaries for the Xilinx ZCU102 development platform. The free BSP enables routing of graphics output to the built-in DisplayPort interface, or to an Ozzy display and I/O module offered by iVeia.

“Since the introduction of the Zynq UltraScale+ MPSoC, Xilinx has seen a lot of customer interest in Android for their advanced designs,” stated Simon George, director, product Marketing — Embedded Software at Xilinx. “Now, with Mentor Graphics embedded solutions, our customers can extend the benefits of the Android ecosystem to their critical designs.”

 
About Zynq UltraScale+ MPSoC

Xilinx’s 16nm FinFET fabricated Zynq UltraScale+ MPSoC competes directly with the Intel/Altera Stratix 10. It features a faster, 1.5GHz quad-core CPU, and more powerful Mali-400 MP2 GPU and FPGA compared to the Zynq-7000.

Zynq UltraScale+ MPSoC block diagram
(click image to enlarge)

Depending on the FPGA level chosen, the UltraScale+ EG ranges from 103K to 1,143K logic cells, 94 to 1,045 flip-flops, and 47 to 523 LUTs. There are also non-MPSoC versions without the ARM block. The UltraScale+ adds two 600MHz Cortex-R5 MCUs with vector FPUs and memory protection units for improved real-time processing. Options include an H.265/264 video codec and a DSP.

Xilinx later added an EV model that is much like the EG, but adds a H.265/H.264 video codec that supports simultaneous encode and decode up to 4Kx2K @ 60fps. However, it has a lower range of logic cells (192K to 504K), and is limited to Gigabit Ethernet connectivity instead of EG options such as 100Gbps Ethernet and 150Gbps Interlaken links.

Last year, Xilinx announced a dual-core “CG” version of the SoC. The CG lacks the EG’s ARM Mali-400 MP2 GPU, and like the EV is limited to GbE connectivity. The six CG sub-models have FPGAs ranging from 103K to 600K logic cells.

 
Further information

The Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit is available now. More information may be found at Mentor’s Zynq UltraScale+ MPSoC product page, which links to a free webinar on the topic.