The UPduino v3.1 is an affordable development platform that showcases the capabilities of the Lattice ICE40 Ultra Plus 5K FPGA. This device is also fully compatible with the open-source graphical design tool, IceStudio.

The UPduino v3.1 is built on a 4-layer PCB and features integration of the Lattice UltraPlus ICE40UP 5K FPGA. This FPGA boasts 5.3K LUTs and comes equipped with 1Mb SPRAM (Single Port RAM), 120Kb DPRAM, and 8 Multipliers, as indicated on the product page.

While the pinout image below illustrates the pin configuration for the UPduino 3.0, it’s important to note that the 3.1 revision incorporates some updates, as mentioned on the product page. These updates include fixing the 12MHz and Ground silkscreen bug and changing the USB filter ferrite bead to a PTC solution.

This last change is aimed at addressing issues related to potential ferrite bead damage if a short circuit occurs between 5V and ground.

 

There are several sources of documentation available for the UPduino, such as the UPduino wiki pages that offer tutorials. Additionally, you can find valuable resources in the tinyVision repository. Moreover, the XarkLabs GitHub repository provides an example project for UPduino using SystemVerilog.

 

Specifications listed for the UPduino-v3.1 include: 

• Memory/Storage:
  • 4MB SPI Flash
• I/O Interfaces:
  • 32x FPGA GPIOs on 0.1” headers
  • 1x RGB LED
• USB:
  • FTDI FT232H USB to SPI Device
• Other Features:
  • On-board 12MHz oscillator
• Power:
  • On-board 3.3V & 1.2V regulators
• Mechanical:
  • 2.2 x 6.2 x 0.5cm

Further information

The UPduino is priced for €27.23 on Lectronz or $30.00 on Tindie.com.