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Linux boots on new “Shakti” RISC-V chip

Aug 1, 2018 — by Eric Brown 6,538 views

[Updated: Aug. 2] — The Shakti project, based at IIT Madras, has booted Linux on its first RISC-V processor. The 22nm FinFET fabricated, 400MHz Shakti chip can run at 1.67 DMIPS/MHz, and will be commercialized by a startup called InCore.

Shakti — the Hindu goddess who personifies creative power — has been enlisted in a variety of creative enterprises, including Unilever’s Project Shakti NGO for empowering rural Indian women. Now Shakti, which means power in Sanskrit, is also the name of a Chennai, India based RISC-V chip development project hosted by the Indian Institute of Technology Madras (IIT Madras) with partial funding from the Indian government. As reported by Fossbytes, the Shakti Processor Project announced it has successfully booted Linux on its first taped RISC-V processor.

The Shakti project was founded in 2014 as an R&D project aimed at building Power ISA chips. The project then shifted to RISC-V, as detailed in this 2016 academic paper. The initiative appears to be the second to successfully boot Linux on a RISC-V processor, following SiFive, which is now shipping its Linux-friendly Freedom U540 processor on a HiFive Unleashed development board. Like SiFive, most other RISC-V projects are focusing on microcontroller unit (MCU) level RISC-V chip for IoT that do not run Linux.

HCL’s daughter board containing Shakti chip (left) and diagram showing test suite with Xilinx Artix-7 board linking to the daughter board
(click images to enlarge)

Intel is collaborating with the Shakti project in fabricating the chips using its 22nm FinFET technology to create a 4 x 4mm die. HCL, meanwhile, has contributed the daughter board containing the processor, which links to a Xilinx Artix 7 board in the test system.


An earlier version of this article incorrectly stated that Western Digital was a sponsor. The main sponsors are the Indian government and the new InCore Semiconductor startup, which will commercialize the chips. AI/ML, IoT, and security applications. The InCore video presentation and document linked to at the end of the article discusses how InCore plans to develop Axon (intelligence/AI/ML), Aegis (security), and Aeon (reliability/IoT), variants of the Shakti processors. Shakti lead designer G.S Madhusudhan is CEO and Neel Gala, the presenter in the video, is the CTO.

The Linux experiment uses a C-Class Shakti chip, which is described as an in-order 6-stage 64/32-bit microcontroller supporting the entire stable RISC-V ISA. The test chip is slower than SiFive’s quad-core, 1.5GHz Freedom U540, with 1.67 DMIPS/MHz Drhystone and 2.2 CoreMark performance. According to an email from Madhusudhan, however, the C-Class design is designed to run between 250MHz to 2.5GHz. However, for the Linux test, the project started with a low-power, 0.75V variant for IoT running at 300-400MHz.

The processor has 16-64KB non-blocking pipelined Instruction and Data caches, as well as optional L2. There’s also an MMU and optional VPU. The initial chip is positioned against Arm Cortex-A35 and Cortex-A55 processors, as well as Intel’s Atom chips.

Shakti die (left) and screen showing Linux booting on it
(click images to enlarge)

In addition to C-Class, the other chip that will appear first on Shakti’s roadmap is the E-Class (PDF), a 3-stage, 32/64-bit microcontroller that supports a subset of RISC-V ISA and runs FreeRTOS. The low power, sub-200MHz chip will compete against Cortex-M MCUs.

The other planned Shakti chips, all of which appear to run Linux, include the 1-4 core, 200MHz to 1GHz I-Class networking and industrial control processor. According to Madhusudhan, the I-Class is a dual/quad issue multi-threaded OO core that can broadly be compared to Cortex-A76 or Intel Core i processors.

Architecture of Shakti processor used in test suite (top) with SoC components shown on the bottom
(click image to enlarge)

Shakti also plans to build an 8-core, quad-threaded M-Class chip for low end server and mobile applications, as well as the 2-16 core, 1.2-3.0GHz S-Class for desktop/server applications. The S-Class processors are superscalar and multi-threaded with a RapidIO based crossbar/ring interconnect and segmented L3 cache. On the high end there’s a 32-100 core H-Class CPU with a performance goal of 3-5 Tflops, as well as an experimental, security-oriented T-Class CPU.

According to a Madhusudhan comment posted on a Ycombinator Hacker News discussion about the Linux test, the project has already entered production to use its first chip to power a control system of an experimental civilian nuclear reactor. As part of the nuclear plant project, Shakti “will also deliver a whole host of IPs including the smaller trivial ones and also as needed bigger blocks like SRIO, PCIe and DDR4,” wrote Madhusudhan.

The lengthy Ycombinator thread was launched by “rwmj” who criticized the design for its lack of the RISC-V Compressed (RVC) variable rate instruction set extension, which “would make it incompatible with all existing Linux distros. Continued rwmj: “These will either have to be recompiled without any Compressed instructions (which increases I-cache pressure on other CPUs that do support it), or we’ll need to ship two versions of everything.”

Others noted that RVC was optional when the first Shakti chip was taped out, and that the RISC-V organization made RVC mandatory without properly warning the larger community. This prompted a larger discussion in which RISC-V was criticized for the way it handled the RVC requirement. Some claimed that this was a harbinger of the same fragmentation that has plagued the Arm ecosystem, while others argued that there were workarounds that were sufficient for this early stage of Shakti development.

Arm proponents have claimed that the open source nature of the RISC-V architecture and governance will doom it to failure due to fragmentation. In early July, Arm posted a website criticizing RISC-V over fragmentation and other issues including cost, security, and design assurance issues. After an uproar both inside and outside Arm, with many critics noting Arm’s own fragmentation issues, the website was removed within a few days.

InCore’s Neel Gala reveals a roadmap for Shakti-based processors

Further information

More information on the Shakti project’s successful Linux boot may be found in this slidedeck. More general Shakti information may be found at the Shakti website and this Shakti C-Class product page. Information on the Linux build may be found here.

More information on InCore Semiconductor and the E-Class and C-Class offerings may be found in this InCore slidedeck (PDF).


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One response to “Linux boots on new “Shakti” RISC-V chip”

  1. Anna says:

    The RISC-V Summit will take place December 3 – 6 at the Santa Clara Convention Center, Santa Clara. To find out more and to register as a delegate visit

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