[Updated: Nov. 1] — Intel formally unveiled its 10nm Tremont core and Lakefield SoC with claims for up to 50 percent faster graphics than Gemini Lake and a tenth of the standby power. Lakefield combines 4x Tremont cores with a 10nm Ice Lake core, Gen11 GPU, and VPU plus a 14nm PCH.

At the Linley Fall Processor Conference in Santa Clara, Calif. last week, Intel released more details on its previously revealed Tremont architecture and Lakefield SoCs. These are the successors to the low-power, Atom-class Goldmont Plus and Gemini Lake, respectively. Intel also announced strong Q3 earnings of $19.2 billion in revenues, beating market expectations by $1.2 billion, and claimed to have boosted production of 14nm wafers by 25 percent in 2019 with a similar increase expected in 2020.

Intel Tremont architecture (left) and ISO-frequency single thread performance benchmarks showing 30 percent average performance boost over Goldmont Plus
(click images to enlarge)
Source: Intel

Intel’s Lakefield SoC will combine 4x Tremont cores, each of which is claimed to be about 30 percent faster than Goldmont Plus, along with an Ice Lake-based, Intel Core class Sunny Cove core and an Intel Graphics Gen11 GPU and other co-processors. All these parts are fabricated at 10nm, but the SoC also integrates a 14nm fabricated PCH I/O chipset using a chiplets heterogeneous SoC design approach and a new 3D stacking technique called Foveros. Intel claims that compared to Gemini Lake, Lakefield offers a 40 percent core area reduction, a 50 percent improvement in graphics performance, and the ability to run on 1/10th the power in standby mode.

Intel will ship its first Lakefield SoCs later this year. Earlier this month, Microsoft announced that it will launch a dual-screen Surface Pro Neo notebook running Windows that will feature Lakefield.

Lakefield’s 3D stacking Foveros design (left) and hybrid power/performance chart
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Source: Intel

Like the Intel Core class Ice Lake Y-series (9W TDP) and U-series (15W) processors, the 4x Tremont cores that will appear on Lakefield SoCs are the first 10nm fabricated Intel processors.

Intel made no mention of its previously announced intention to release more powerful desktop Ice Lake processors based on its troubled 10nm process, although it recently claimed that it has solved its 10nm problems and that 10nm desktop parts were indeed on the way. This week, Intel CEO Bob Swan announced plans to build additional 10nm chips including Xeon processors, an AI Inference Accelerator chip, and a discrete GPU.

Swan also briefly mentioned an upcoming 10nm-fabricated “5G base station SoC.” This is the previously teased Snow Ridge networking SoC built on Tremont cores. Farther below, we’ll take a brief look at a Snow Ridge block diagram that leaked last month.

 
Inside Tremont

Tremont offers several advancements in ISA (instruction set architecture), microarchitecture, security, and power management over the 14nm Goldmont Plus, says Intel. As shown in the chart farther above, Intel is claiming an average of about 30 percent ISO-frequency single thread performance boost over Goldmont Plus, depending on a customer’s selected power/performance tradeoff. At maximum power, the chart shows about a 65 percent boost.

According to AnandTech, the impressive 30 percent ISO-frequency boost benchmarks were based on an early version of Tremont and are not well documented. There are no specifics on clock rates, TDPs, or die footprints. Intel did, however, note that the Lakefield SoCs that will integrate the Tremont cores can go to as low as about 7W TDP. Intel had previously suggested Lakefield could go as low as a 3-5W. AnandTech speculates that Tremont-based SoCs may not be able to match the lower 6W and under TDPs found on the lower-end models of earlier Atom processors.

In multi-core implementations, all the Tremont cores must be similarly clocked, says AnandTech. However, each core can be given varying levels of lower c-states to reduce power consumption when not in use.

Performance improvements are based on a 6-wide (2×3-wide clustered) out-of-order decoder located in the front end, which “allows for a more efficient feed to the wider back end,” says Intel. The back-end uses a 10-wide execution port architecture. The wider front-end, which is twice as wide as the 3-wide Goldmont Plus, enables “more instructions in flight, larger caches, bigger buffers, bigger TLBs, more execution ports, and support for more instructions,” says AnandTech. The front-end design is more accurate described as dual 3-wide decode engines rather than as a 6-wide engine, says the story.

Tremont front-end architecture showing 6-wide (2×3-wide clustered) out-of-order decoder
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Source: Intel

According to an ExtremeTech analysis of the announcement, Intel went with the unusual 6-wide design to avoid the use of a micro-op cache, which would take up too much die space. By comparison, the Ice Lake based Sunny Cove core on the Lakefield SoC has a 4-to-6 wide decode that supports micro-op cache.

L1 cache has been increased from 24KB to 32KB, and a shared L2 cache can range from 1.5MB and 4.5MB, depending on user preference. Tremont has borrowed prefetchers and branch predictors from the Core architecture, although the implementations are not identical. There is no performance penalty for L1 prediction, claims Intel.

Tremont features Intel’s Speed Shift technology, which was previously available only on Core designs. This lets the CPU control its own clock transitions in hardware more efficiently than possible with software. Intel also added a Total Memory Encryption function to Tremont to boost security.

 
Inside Lakefield

The Lakefield SoC will be available in a 12 x 12mm POP package. The 10nm fabricated “compute” die layer in the 3D stacking Foveros design provides four Tremont (TNT) cores for low-power tasks plus the higher-powered Sunny Cove (SNC) core, which is optimized for high-speed single thread performance and “bursty” workloads.

Intel Lakefield architecture
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Source: Intel

The Lakefield compute layer also includes a 64-EU Intel Gen11 GPU and a Gen 11.5 VPU with up to [email protected] and [email protected] video. There’s also a separate “media core” capable of handling [email protected] and [email protected] video decoding, as well as an IPU that supports up to a single 16-megapixel camera or up to 6x connected cameras at once.

A separate base layer die shown on the bottom of both of Intel’s Lakefield architecture diagrams, is the 14nm PCH part for I/O control called the base layer. This includes support for interfaces including PCIe Gen3, USB 3.0, I2C, and the upcoming I3C sensor bus interface, which offers lower power consumption and greater performance, including a minimum data rate of 10Mbps.

As with Tremont, Intel does not list specific clock rates, but one slide confirmed a 7W TDP in showing Lakefield graphics performance at 7W of up to 50 percent faster than Gemini Lake. Intel also lists 2.x mW standby power, which is 1/10th the standby of Gemini Lake.

Intel’s Lakefield dual display AEP
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Lakefield will be delivered on a “LKF dual display AEP” board for dual foldable display notebooks and thin clamshells. The board is smaller than earlier AEP boards, measuring only 123 x 30 x 0.6mm.

 
Snow Ridge leaks

Intel offered no new details on the 10nm Snow Ridge SoC for 5G basestations that Intel briefly announced in January at CES as a server and edge computing SoC. The processor is widely speculated to use Tremont cores. Intel had originally projected a 2Q 2019 release, but in a July earnings call amended that to 1Q 2020.

Leaked block diagram for Intel Snow Ridge
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Source: Tom’s Hardware

Last month, Tom’s Hardware reported on a Snow Ridge block diagram that was leaked in a tweet by Intel platform engineer Mark Ermolov. The diagram shows six “Atom Core Tiles,” which the story suggested might signify a 12-core design with two cores per tile. Ermolov confirmed in his tweet that the SoC uses Tremont cores.

The preliminary Snow Ridge block diagram shows an Ethernet controller and support for dual-channel DDR4 and PCIe Gen 3. The SoC is unusual in that it supports a mesh architecture rather than the traditional ring bus.

The block diagram suggests that Snow Ridge will lack a high-powered Sunny Cove or GPU. A note says this is only one possible configuration, so there may be more or fewer cores.

So far, Intel has made no promises for other Tremont-based SoCs with smaller core counts and lower TDPs for embedded. AnandTech suggests that it’s possible Intel may not choose to do so as it refocuses the Atom class on performance — presumably with higher, more Core-like prices and margins. Intel lists a Gracemont architecture on its roadmap that will follow Tremont.

Intel has had problems with some Atom-based models, including the Atom C2000, the forerunner of the more widely deployed, server-class Atom C3000. The C2000’s circuit degradation flaw has since been fixed, but last month, Intel announced a similar problem that afflicts certain Apollo Lake/Goldmont based Celeron N3350, J3355, J3455, and Pentium N4200 SoCs.

After stating it would discontinue these parts, a few days later, Intel revised that announcement. As reported by ExtremeTech, Intel switched to stating that customers expecting to use the processors for up to 15 years might encounter problems using B1 stepping parts, but could switch to F1 steppings. Customers using the SoCs for more typical 7-year lifespans do not need to worry, said the chipmaker.

 
Further information

Intel’s Lakefield SoC with Tremont cores will launch to customers by the end of the year, with products due in 2020. More information may be found in Intel’s Tremont announcement and Tremont slidedeck (PDF), as well as a brief Lakefield announcement and Lakefield slide deck (PDF).