SiFive announced free downloads and tools for rapid evaluation of its “fully synthesizable” RISC-V based E31 and E51 Coreplex IP on a $99 FPGA dev board.

The 64-bit RISC-V ISA (instruction set architecture) was developed at the University of California, Berkeley in 2010, and subsequently became the basis of a University of Cambridge sponsored lowRISC open-source SoC project in mid-2014.

HiFive1 eval board

Last July, San Francisco based, VC-funded startup SiFive, founded by several of RISC-V’s inventors, unveiled its first two RISC-V based embedded SoCs. In November, SiFive launched a successful Crowd Supply campaign for an Arduino-ready HiFive1 development board, built around the company’s 320MHz, RISC-V based FE310 SoC.

Also in November, Bucaramanga, Colombia-based Onchip launched an Arduino-compatible, RISC-V based Open-V MCU and development kit on Crowd Supply. Additionally, rumors emerged that Samsung may be developing a RISC-V based SoC targeting IoT applications, although the company has not shown up on the RISC-V members list, which has now grown to 60 corporate and educational entities. These days, RISC-V is increasingly mentioned as a potential alternative to proprietary architectures like x86, ARM, PowerPC, and MIPS.

 
RISC-V Coreplex IP ready for “hassle-free” evaluation

This week, SiFive announced a new “study-evaluate-buy” purchase process, that lets developers “get their hands on Coreplex IP RTL in a matter of minutes.” The immediately downloadable E31 Coreplex and E51 Coreplex IP RTL is described as “fully synthesizable and verified soft IP implementations that scale across multiple design nodes, making them ideal for your next SoC design.” On its Coreplex IP evaluation web page, SiFive describes the IP evaluation and purchase as being fast, NDA-free, and with a pricing model that is not based on royalties.

64-bit E51 Coreplex (left) and 32-bit E31 Coreplex block diagrams
(click images to enlarge)

SiFive says its 32-bit E31 Coreplex is “well suited to replacing [ARM’s] Cortex-M3 and Cortex-M4,” and claims that it “provides even higher performance without sacrificing area or power.” For its part, the mostly-similar 64-bit E51 Coreplex is said to offer 64-bit performance at a 32-bit price, power, and area.

Comparison of E51 Coreplex and E31 Coreplex
(source: SiFive)

	E51 Coreplex		E31 Coreplex
	28nm HPC	55nm LP	28nm HPC	55nm LP
Core-only area	0.046 mm2	0.083 mm2	0.026 mm2	0.050 mm2
Coreplex area	0.23 mm2	0.66 mm2	0.17 mm2	0.55 mm2
Frequency	Typical: 1.5 GHz; Worst: 900 MHz	Typical: 540 MHz; Worst: 320 MHz	Typical: 1.5 GHz; Worst: 900 MHz	Typical: 540 MHz; Worst: 320 MHz
Performance (typical; DMIPS)	2700 total	972 total	2415 total	869 total
Core-only pwr (DMIPS/mW)	125	78	150	95
Coreplex pwr (DMIPS/mW	36	15	41	16

The E51 Coreplex is said to be well suited for use as a system or host control subsystem within a larger 64-bit SoC, and its applications are expected to include SSD controllers and network processors that require 64-bit compute power “without the requirement of virtual memory or full-featured operating systems.”


Digilent Arty board
(click image to enlarge)

Evaluation of SiFive’s RISC-V based E31 Coreplex or E51 Coreplex IP involves downloading the desired core’s FPGA bitstream and installing it onto a $99 Digilent Arty board, which is based on Xilinx’s Artix-7 FPGA. Note, however, that before you can download a Coreplex bitstream, you’ll need to create a SiFive account and agree to SiFive’s 3600-word “Developer Program Agreement,” which contains the terms “confidential” or “confidentiality” 31 times.


SiFive Freedom Studio development tool
(click image to enlarge)

Once you’ve evaluated a Coreplex bitstream, the licensing process consists of choosing and customizing the desired Coreplex IP, agreeing to a 7-page license agreement that’s said to involve “no restrictive NDAs,” and submitting your order. Then, after “several business days” you’ll receive your licensed IP.

 
SiFive receives additional funding

In related news, SiFive announced today that it has raised an additional $8.5 million of funding. The Series B round was led by Spark Capital, and also included participation from Osage University Partners and earlier investor Sutter Hill Ventures. This brings the company’s total investment to $13.5 million.

“This investment will enable our continued growth for years to come, and will allow SiFive to further establish that alternatives really matter in an era where traditional silicon vendors no longer are the most innovative in the industry,” said Jack Kang, vice president of product and business development at SiFive.

 
Further information

SiFive’s “study-evaluate-buy” Coreplex IP technology evaluation package is available here. Pricing for licensing the E31 Coreplex and E51 Coreplex IP was not stated, other than the fact that it does not involve royalties. Additional details regarding the RISC-V ISA may be found at the RISC-V Foundation website. SiFive’s successfully funded open source, Arduino-compatible, HiFive1 RISC-V Dev Kit is available for $59 at Crowd Supply.