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Compulab’s embedded Tensor-PCs take modularity to the extreme

May 4, 2020 — by Eric Brown — 1442 views

CompuLab is launching a line of fanless “Tensor-PC” systems starting with an Intel 9th Gen “I20A” model with a choice of multiple sizes and enclosures plus a variety of optional open source “Tensor Element” modules for storage, power, I/O, and networking.

Compulab is re-inventing its fanless, embedded PC product line with a highly modular Tensor-PC architecture, starting with an Intel 9th Gen Coffee Lake Refresh based Tensor-PC I20A system due this fall. The x86-based Tensor-PC systems will run Linux and Windows.

The Tensor-PC I20A will replace Compulab’s similarly sized, 7th Gen Kaby Lake based IPC3. There will also be a lower-end Tensor-PC model for up to 10W TDP processors that replaces the compact, Apollo Lake based Fitlet2 and a high-end edge server system for up up to 100W CPUs that replaces the Airtop3 A fourth Tensor-PC will fall in in between the IPC and Airtop tiers aimed at up to 60W processors.



Tensor-PC I20A with small and large enclosure options
(click images to enlarge)

All the Tensor-PC systems will support the same Tensor Elements (TELs) — modular extensions for I/O, storage, power supplies, and networking — into Compulab’s new TRIP (Tensor Ribbon Port) interfaces. The ribbon-connected TELs will be supported with open schematics to encourage third-party development.

The initial Tensor-PC I20A model is equipped with up to hexa-core 9th Gen Coffee Lake Refresh Core or Xeon CPUs with up to 25W TDP, accompanied by an Intel CM246 chipset. The I20A supports up to 64GB DDR4 via dual channels and offers 3x display interfaces. Up to 37 PCIe 3.0 lanes are expressed via TRIP interfaces.



Tensor-PC I20A mainboard, front and back
(click image to enlarge)

The Tensor-PC I20A is further equipped with a 12V power input, an FPGA for sequencing and control, an RTC, and a TPM 2.0 chip. The 150 x 130mm I20A mainboard is available with 18 enclosure types (see farther below). Compulab is not planning to market the mainboard as a separate SBC product, but will sell SBC-only packages by special request. Each Tensor-PC system will have its own mainboard with different sizes and features.

 
Background: a brief survey of modular I/O

The diversity of applications in embedded computing demand an abundance of variety. Many vendors address the challenge of meeting different requirements by releasing multiple iterations on a single model with relatively minor differences, such as many of Aaeon’s Boxer and Axiomtek’s eBox computers. Many vendors also offer hardware customization services for volume customers.

Another popular approach to the diversity challenge is to offer modular expansion via mini-PCIe, M.2, and for the larger AI boxes designed for Nvidia cards, full-sized PCIe slots. Some adopt other industry standards, like Adlink’s use of MXM3 or the SUMIT interfaces found on some Ibase and Vecow systems.

Many vendors also offer proprietary, customized expansion interfaces based on PCIe or USB that are supported by their own modules. Cincoze, for example, offers CFM and CMI slots, WinSystems has IO80, Neousys has MezIO, EFCO has IOM1, and Compulab has provided a homegrown FACE (Function And Connectivity Extension) interface.

 
TRIPs and TELs

With Tensor-PC, Compulab has replaced FACE interfaces and modules with TRIPs and TELs, which are based on the more compact M.2 form factor, enabling many more interfaces on a single SBC. For example, while IPC3 has a single FACE interface, the Tensor-PC I20A has the equivalent of eight.



Tensor-PC I20A mainboard detail view showing yellow and red TRIPs (left) and block diagram
(click images to enlarge)

Like FACE, most TRIP interfaces and TELs support 4x PCIe lanes plus single USB 2.0 and SMBus signals. These include all the TRIPs identified with numbers on the detail view above, which are further identified by their yellow RLMs (Ribbon Latching Mechanisms). TRIPs with red RLMs identified by letters (S, M, U, SV, PWR) usually lack PCIe. They have a different pinout and are based on USB, GPIOs, SMBus, or other interfaces.

Any TEL designed for a yellow RLM TRIP can be plugged into any yellow TRIP. The red TELs, however, must plug into the appropriate TRIP. Each TRIP has its own LED, which confirms a compatible TEL is enabled. The system’s firmware identifies the type of TEL and ribbon used in each interface and allows users to enable or disable each TEL. It also identifies mismatches such as a TEL designed for a TRIP with a yellow vs. a red RLM.

One difference from most other modular I/O schemes, including FACE, is that TELs are not directly plugged in, but attached by ribbon connectors. Compulab chose ribbons to free TELs from the size and shape restrictions posed by direct connections.

Together with Tensor-PC’s modular enclosure and coastline schemes described farther below, ribbons enable the external ports to be placed or moved to different positions, for example, if a chosen mounting mechanism interferes with the default port placements. Ribbons make it easier to choose different enclosure sizes and types to optimize for space and cooling. A variety of ribbon lengths are available, from 10cm to 30cm, and RFCs (Ribbon Folding Clips) help reduce clutter and tangling.



Dual-GbE TEL-LAN2 module (left) and connected to Tensor-PC I20A mainboard with clipped ribbons
(click images to enlarge)

Compulab expects to have about 40 TELs for launch, with more on the way. The first 29 are listed below. The TELs can be divided into five main categories: storage, power, I/O, networking, and extension (SPINE). The SPINE TEL modules provide established expansion interfaces such as mini-PCIe, M.2, PCIe, as well as an MCU-based TEL-SV for out-of-band management and monitoring.


Available TELs
(click images to enlarge)

Storage TELs include NVMe and up to 4x SATA interfaces, and power TELs offer options like wide-input and load-balancing. Networking TELs include up to 4x GbE and 2x 10GbE, as well as PoE and SFP+ add-ons. I/O TELs comprise a variety of USB and DP configurations plus audio, serial, CAN, and GPIO.

All schematics, bill-of-material, and production and mechanical design files for TELs are openly published. Third parties that design their own TELs are not required to open source their own designs.

 
Tensor-PC enclosures

The Tensor-PC design enables ports and slots to be placed on up to four sides (coastlines) of the enclosure. Compulab has yet to decide to what degree customers can choose port placement or whether a variety of different coastline templates will be available. According to CompuLab’s Irad Stavi, potential scenarios range from a DIY customer purchasing a barebones system with selected TELs and making their own cutouts to volume customers specifying a specific layout.

To ease port placement design, Compulab has come up with an 11.15mm measurement unit called TPU (Tensor Panel Unit). Customers will also receive extensive documentation on the TELs along with an interactive spreadsheet or a simple web tool for making placement choices, said Stavi.

The Tensor-PC I20A will be available in 18 different enclosure types, all of which attach the mainboard directly underneath the top of the enclosure. As shown in the matrix graphic below, the enclosures differ according to width, height, and cooling design. You can choose between 200m or 300mm enclosure widths and three heights: 25mm, 35mm, and a dual-layer compartment. The latter has a second layer for customers who need room for a lot of large TELs.



Tensor-PC enclosure matrix showing 18 enclosures with different mixtures of width, height, and cooling
(click image to enlarge)

These configurations can then be separated into different cooling systems, based on the Fitlet design. You can have a flat cover, a 10mm cooling rib, or a 20mm rib that supports extended (TE) and industrial (TI) temperatures.

The Tensor-PC I20A has several cooling advantages compared to the IPC3, says Compulab. These include heatpipes for CPU cooling instead of using a solid block, as well as improved thermal headroom and interface materials and an automatic thermal shutdown feature called TIPP (Industrial Temeprature Predictable Performance). Customers can also improve cooling by matching the footprint of their TEL configurations with the enclosure size and cooling type. CPU and power settings can be preset by Compulab for the selected enclosure and then changed by users.

 
Benefits of modularity

Like other modular I/O schemes, Tensor-PC’s TRIP/TEL architecture can extend the lifespan of computers while reducing electronic waste. The TELs’ wider array of functionality should extend these benefits even further while also reducing the downtime caused by RMAs (Return Merchandise Authorizations), says Compulab. If you have a faulty TEL, you can replace it rather than send back the entire system for an RMA. Larger customers will likely keep extra TELs in stock for fast swap-outs.

The Tensor-PC architecture omits one common approach to modularity: separating the compute module from the carrier board to enable processor and memory upgrades. Although CompuLab has a line of Arm-based compute modules, such as the i.MX8X-based CL-SOM-iMX8X, it has no COM Express modules. In essence, the large, but COM-like SBC is the compute module. According to Stavi, COM Express does not support the required granular modularity demanded of the Tensor-PC I/O scheme.

 
Further information

The Tensor-PC I20A will begin sampling to resellers and key customers in May, followed by volume production for business customers in Q3 2020 and single-product sales in Q4. Additional Tensor-PC models will follow in the years to come. No pricing was available. You can fill out a form to indicate your product needs here. More information should eventually appear on Compulab’s website.

 

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One response to “Compulab’s embedded Tensor-PCs take modularity to the extreme”

  1. lcdi says:

    Hi
    good news as a happy compulab product owner
    I ‘m hoping for rack mounted 19’ solution. Any chance ?
    best regards

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