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Codasip unveils Linux-ready RISC-V cores with AI and multi-core support

Dec 7, 2020 — by Eric Brown 4,410 views

Codasip announced three new Linux-friendly, 64-bit RISC-V cores: an edge AI oriented A70XP core with RISC-V P extensions and SMP-ready, up to quad-core A70X MP and A70XP MP models.

In July, Codasip announced a Linux-oriented Bk7 core IP architecture, which later appeared in a A70X design that is now available for licensing. The company has now unveiled three new Linux-ready core designs with the same Bk7 architecture that will arrive in Q1 2021.

A70XP MP architecture (left) and Codasip’s RISC-V cores
(click images to enlarge)

The A70XP adds a SIMD (single instruction, multiple data) unit that executes RISC-V P extension instructions with single-cycle latency. Multi-cycle instructions are pipelined to allow one to be executed every clock cycle. The extensions are said to enable audio encoding/decoding, sensor fusion, computer vision, and edge AI/ML applications.

Andes Technology offers P extension support on its 45-series cores including the recent AndesCore A45MP and AX45MP via an optional DSP. The similar naming scheme between the Codasip and Andes cores are confusing, but logical: In both cases, the A stands for application processor and the MP stands for multiprocessor (multi-core) support.


Codasip does not explain the difference between the new, multi-core ready A70X-MP and A70XP-MP, but judging from the naming scheme, the A70X-MP is a multi-core ready version of the A70X and the A70XP-MP is the multi-core version of the new P-extension enabled A70XP. Both MP processors support clusters of up to four cores in an SMP (symmetric multi-processor) configuration. They also offer configurable L1 and L2 caches with a scalable microarchitecture.

All of Codasip’s A-series cores are 64-bit, single in-order, 7-stage pipeline designs that provide a Floating Point Unit (FPU) and Atomic instructions. They all integrate a Memory Management Unit (MMU), use an AXI external interface, and support Machine, Supervisor, and User privilege modes. (For more details, see our earlier Codasip Bk7 report.)

The A-series cores join Codasip’s non-Linux Low Power Embedded and High Performance Embedded cores, which use the Bk3 and Bk5 microarchitectures. All the RISC-V cores were designed with Codasip Studio. In October, Codasip announced Codasip Studio 8.4, featuring WFI automation, interconnect, and parametrized RTL features.

Further information

The three A70XP, A70X MP, and A70XP MP cores will be available in Q1 2021. More information may be found in Codasip’s announcement and RISC-V page.

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