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Zynq UltraScale+ vision kit has a 4K ISP plus GigE and USB3 Vision cores

May 11, 2020 — by Eric Brown — 644 views

MYIR’s $599 Vision Edge Computing Platform (VECP) Starter Kit runs Linux on its Zynq UltraScale+ based MYC-CZU3EG module and integrates a CSI-connected Sony camera plus [email protected] ISP, GigE Vision, and USB3 Vision IP cores.

Last July, MYIR announced a MYC-CZU3EG CPU Module based on Xilinx’s quad -A53, FPGA-equipped Zynq UltraScale+ MPSoC along with a MYD-CZU3EG Development Board. Now the company has combined the module with a smaller new MYD-CZU3EG-ISP dev board and an 8.42-megapixel Sony IMX334LLR camera into a Vision Edge Computing Platform (VECP) Starter Kit. The Linux-driven kit supports [email protected] video processing for machine vision, industry, IoT, and medical applications.



Vision Edge Computing Platform (VECP) Starter Kit and image processing flow showing ISP and GiG-E and USB3 Vision IP cores
(click images to enlarge)

The 60 x 52mm MYC-CZU3EG module defaults to a Zynq UltraScale+ XCZU3EG variant that features a 667MHz Mali-400 MP2 GPU. The VECP Starter Kit combines this model with a Linux stack that is different than the one listed for the module on its own. You get Linux 4.14 with Boot.Bin, a gcc 7.2.1 cross-compiler, a file system, and more, all provided with source code.

The MYC-CZU3EG CPU is loaded with 4GB DDR4, 4GB eMMC, and 128MB QSPI flash and features GbE and USB PHYs. The 3.3V, 0 to 70°C-ready module has a PMIC, watchdog, clock generator, and 4x LEDs.



MYC-CZU3EG detail view (left) and available Zynq UltraScale+ MPSoC models
(click images to enlarge)

Dual Samtec 0.5mm-pitch 160-pin headers express I/O. FPGA-connected I/O on the MYC-CZU3EG includes 156 user PL I/O pins, 4x PS GTR transceivers with 2x GTR reference clock inputs, and 4x PL GTH transceivers with 1 GTH reference clock input and PS MIOs.

 
VECP Starter Kit (MYD-CZU3EG-ISP)

The new MYD-CZU3EG-ISP board used by the VECP Starter Kit has a smaller 106.7 x 70mm footprint than the MYD-CZU3EG carrier. It lacks many of its features, including SATA, CAN, DisplayPort, LCD, PCIe, Arduino, PMod, FMC, and an optional SFP optical networking cage. However, it adds a second GbE port, an I/O expansion interface, and a MIPI-CSI interface for the Sony camera mounted on the back.



VECP Starter Kit’s MYD-CZU3EG-ISP board, front and back
(click images to enlarge)

The 8.42-megapixel Sony IMX334LLR (PDF) camera is accompanied by an ISP core that can process 3840 x 2160 video at 30fps with “ultra-low delay video transmission at maximum 0.7ms,” says MYIR. The camera has a 2.0 μm × 2.0 μm pixel size with 12-bit ADC resolution and supports up to 120fps frame rates.


VECP Starter Kit with fan and block diagram
(click images to enlarge)

The VECP Starter Kit supports Bayer, YCbCr and RGB input video formats and can output video over FPGA-connected HDMI, USB 3.0 device, and GbE ports. The board provides a USB3 vison IP core and a GigE vision IP core that supports Machine Vision GenICam V2.4.0 and user-defined XML

The MYD-CZU3EG-ISP feature set includes USB 3.0 host and FPGA-connected USB device ports, a micro-USB serial console port and dual GbE ports: one for the Arm block and the other for the FPGA.



MYD-CZU3EG-ISP detail view
(click image to enlarge)

Other features include a microSD slot, an HDMI port, JTAG and fan connectors, and a boot switch. The 12V/2A board has a 50-pin FPC I/I connector and supports 0 to 70°C temperatures. The VECP Starter Kit adds HDMI and USB cables, a power adapter, a fan, a 16GB microSD card, and a documentation disc.

 
Further information

The VECP Starter Kit is available for $599, including the MYC-CZU3EG module. More information may be found in MYIR’s announcement and product page.

 

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