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SiFive unveils new RISC-V designs, including two Linux-ready models

Oct 31, 2018 — by Eric Brown — 2985 views

[Updated: Nov. 13] — SiFive announced a new line of RISC-V based, SiFive Core IP 7 Series cores, including the Linux-friendly, Cortex-A55 like U74 and quad-core U74-MC, a variant that adds an MCU for real-time, latency sensitivity.

SiFive has launched its second generation of chip designs that use the open source RISC-V architecture, including two new Linux-ready U7 models. All the IP 7 Series cores “offer efficient performance and optimized power consumption, appropriate for supporting smart offloads of data center workloads as well as those of extremely power efficient edge devices,” says SiFive.

The new IP 7 processor designs include:

  • U74 — Linux-ready, Cortex-A55 like, 2.5 DMIPS, single-core with 128KB L2
  • U74-MC — Linux-ready, Cortex-A55 like, 2.5 DMIPS, quad-core with 2MB L2 and S7 monitor chip for real-time
  • E76 — Cortex-M7 like, 2.3 DMIPS, single-core
  • E76-MC — Cortex-M7 like, 2.3 DMIPS, quad-core with 2MB L2
  • S76 — Cortex-R8 like, 2.5 DMIPs, single-core
  • S76MC — Cortex-R8 like, 2.5 DMIPs, quad-core with 2MB L2

The IP 7 chips provide 64-bit memory addressability for real-time processors and in-cluster “coherent combination of real-time processors and application processors,” says the company. The IP 7 family supports 8+1 cores per cluster, including heterogenous mixing of all four IP processor series in up to eight-processor clusters.



SiFive U74 (left) and U74-MV block diagrams
(click images to enlarge)

The IP 7 Series provides enhanced determinism for hard, real-time constraints, as well as functional safety provided through various fault tolerance mechanisms, says SiFive. The chips use an 8-stage in-order pipeline, “which introduces microarchitectural features to prevent side channel attacks that enable a robust secure processor implementation,” says the company.

As RISC-V chips, the designs are open source and customizable. Unlike Arm and x86, RISC-V is purpose-built for the latest technologies and applications and is unburdened with legacy code.


HiFive Unleashed

SiFive’s Cortex-A55 like U7 core designs follow its similarly Linux-compatible, 64-bit U5 series cores used in its Freedom U540 a quad-core, 1.5GHz RISC-V SoC. The U540 powers SiFive’s open spec HiFive Unleashed SBC. SiFive’s U540 was not only the first Linux-ready RISC-V chip, but the first multi-core SoC featuring the open source RISC-V ISA. Another Linux-supported RISC-V chip is the Shakti chip which is partially funded by the Indian government.

 
Inside the U74 and U74-MC

The Linux-ready U74 and U74-MC provide “a highly configurable memory architecture for domain specific customization,” says SiFive. The more advanced, quad-core U74-MC model adds one of the new S7 MCU cores as a fifth monitor core to enable real-time, latency sensitive applications such as “5G baseband processing, enterprise class storage for FAST or BIG data, and multi-mode sensor fusion for AR/VR/SLAM applications.”

The Linux-compatible U74 and U74-MC both provide 2.5 DMIPS/MHz and 4.9 CoreMark/MHz performance, which SiFive equates with Arm’s Cortex-55 cores. The U7 series chips provide 32KB/32KB L1 caches, Sv39 virtual memory support, and 8-region physical memory protection (PMP).

By comparison, the Cortex-A55, lacks integrated PMP, and unlike the U7 chips, it offers 16-bit instruction support only in 32-bit AArch32 T32 Mode. In addition, memory mapping is customizable with the U7 designs instead of fixed on the -A55, says SiFive.

The main difference between the U74 and U74-MC is that the MC version is quad-core instead of single-core. It also adds a Cortex-R8 like S7 chip as a monitor core and supplies a much larger L2 cache (2MB vs. 128KB). In addition, the U74-MC adds superior real-time capabilities, including the ability to configure the L2 cache and L1 instruction cache to be configured into high-speed deterministic SRAMs.

The U74-MC instruction set also differs in that it features an RV64IMAC while the U74 lists only an “S+U+M Mode.” Although only the U74-MC page mentions debug with instruction trace and only the U74 pages lists CLIC and PLIC timer and interrupt features, both block diagrams indicate support for all these features. The interrupt controller, which is pre-integrated on the U74, is listed as optional on the U74-MC. By comparison, this is a separately licensed IP on the Cortex-A55.

 
E7 and S7 microcontroller designs

The U7 chips are joined by two MCU-like IP 7 Series designs. The 32-bit E7 series — the E76 and E76-MC — compares with the Cortex-M7. The 64-bit S7 series, which includes the S76 and S76-MC, compares with the Cortex-R8. The E7 and S7 microcontrollers support real time embedded and bare metal operating systems.



E76-MC (left) and S76-MC block diagrams
(click images to enlarge)

As with the U7 chips, the E7 and S7 designs are available in quad-core MC versions that supply optional 2MB of L2. By comparison, the Cortex-M7 and Cortex-R8 provide no integrated L2 and the Cortex-M7 lacks multi-core support. Unlike the Cortex-R8, the E7 and S7 support heterogeneous combinations with Linux-ready applications processors (U7 and Cortex-A, respectively).

The E7 and S7 models offer the advantage over their Cortex rivals of providing customizable — rather than fixed — memory mapping. In addition, the E7 offers 8-stage instead of the Cortex-M7’s 6-stage pipeline depth, and the S7 is 64-bit compared to 32-bit for the Cortex-R8.

The E7 and S7 designs follow SiFive’s earlier, 320MHz FE310 MCU based on its original Freedom E300 design. The FE310 SoC appeared last year in an Arduino ready HiFive1 dev kit and a wireless-enabled Arduino Cinque board.

 
Further information

The SiFive Core IP 7 Series core designs appear to be available now. More information may be found at the SiFive product page, which includes separate pages for its IP 7 IP designs as well as older processors.
 

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