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SDR dev kit builds on Zynq UltraScale+ RFSoC

Sep 17, 2019 — by Eric Brown — 1291 views

Avnet has launched an “RFSoC Development Kit” that extends Xilinx’s eval kit for its Linux-powered, Zynq UltraScale+ RFSoC. The kit adds a Qorvo 2×2 Small Cell RF front-end for SDR prototyping and integrates MATLAB and Simulink.

Xilinx launched its 5G-focused Zynq UltraScale+ RFSoC variant of its Arm/FPGA hybrid Zynq UltraScale+ MPSoc last year and then announced a Gen3 update in early February. Avnet has now launched an extended version of the Linux-driven Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit that adds a Qorvo 2×2 Small Cell RF Front-end 1.8GHz Card and MATLAB support for software-defined radio (SDR) prototyping,

Avnet RFSoC Development Kit with Avnet RFSoC Explorer for MATLAB and Simulink shown at left
(click image to enlarge)

The Avnet RFSoC Development Kit provides a “rapid, comprehensive RF Analog-to-Digital signal chain prototyping platform” that enables developers to “characterize data converters before SoC software is developed and perform over-the-air testing in MATLAB with live RF signals,” says Avnet.

Before we dig in too deep, note that the kit costs $9,495 compared to $8,995 for the Xilinx eval kit by itself. Yet developers who want to “jumpstart RF-Class analog designs for wireless, cable access, early-warning (EW) and radar, and other high-performance RF applications” may well find it worth the price.

Avnet makes no mention of software support aside from the bundled Avnet RFSoC Explorer for MATLAB and Simulink software, but the Zynq UltraScale+ RFSoC runs Xilinx’s PetaLinux along with other Linux distros. Avnet, by the way, just boosted its embedded Linux software expertise by acquiring Witekio, formerly known as Adeneo Embedded.

Zynq UltraScale+ RFSoC

Like the MPSoC version of the Zynq UltraScale+, which Avnet uses to power its 96Boards CE form-factor Ultra96 SBC, the Zynq UltraScale+ RFSoC combines a Linux-driven Arm block of 4x 1.33GHz Cortex-A53 cores with dual 600MHz Cortex-R5 MCUs and programmable FPGA logic. The main difference is the addition of an RF converter subsystem that supports 8x 12-bit 4.096GSPS ADCs, 8x 14-bit 6.554GSPS DACs, and 8x soft-decision forward error correction (SD-FECs).

Zynq UltraScale+ RFSoC block diagram and specs
(click images to enlarge)

Avnet’s kit uses the XCZU28DR-2FFVG1517e RFSoC model, which is one of the original 4GHz Gen1 designs. A Gen2 version that began shipping this summer advances to 5GHz and the Gen3 model due by the end of the year goes to 6GHz (see table above). The Gen1 model has the same programmable logic as the newer 5G-compatible versions, including 930 logic cells and 4,272 DSP slices. However, its PCIe x16 interface is PCIe Gen3 rather than the RFSoC Gen 3’s PCIe Gen4 interface.

Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit

The Avnet kit is built around the Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Board, which ships with 4GB DDR4-2400 for the Arm subsystem and 4GB DDR4-2666 for the FPGA. The board integrates a reference PLL (LMK04208) and RF PLLs (LMX2594) to generate RF-ADC and RF-DAC sample clocks.

Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Board (left) and full kit
(click images to enlarge)

The Xilinx eval board provides a ganged SFP28 cage to support up to 4x SFP/SFP+/zSFP+/SFP28 modules for communications. There’s also a standard GbE port, a DisplayPort 1.2, a USB 3.0 port, a microSD slot, and an M.2-based SATA interface. Other features include 8x GPIO, 2x PMOD headers, JTAG debug and config circuitry, and a variety of push buttons switches, clocks, and other features as shown in the detail view below.

Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Board detail view
(click image to enlarge)

The Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Board includes an FPGA Mezzanine Card (FMC+) interface for I/O expansion including 12x 33Gbps GTY transceivers and 34 user defined differential I/O signals. The full kit also includes an XM500 RFMC balun transformer add-on card with 4x DACs and 4x ADCs “to baluns 4x DACs/4 ADCs to SMAs,” says Xilinx. Various cables are also included along with an adapter for the 12V input.

Avnet RFSoC Dev Kit with Qorvo 2×2 Small Cell and MATLAB

The Avnet RFSoC Development Kit combines the Xilinx eval kit with a Qorvo 2×2 Small Cell RF Front-end 1.8GHz Card for prototyping of SDR for small cell applications using OTA. Developed in partnership with Avnet, the Qorvo card provides the Qorvo QPA9903, a 0.5 Watt “high-efficiency linearizable” power amplifier.

Avnet RFSoC Development Kit with Qorvo add-on (left) and conceptual diagram
(click images to enlarge)

The Qorvo card provides dual channels, each with Tx, Rx, and DPD (Digital Pre Distortion) observation paths. There’s also default tuning to an LTE 1800MHz FDD System and a Fast Rx Digital Step Attenuator and receiver protection circuit. In addition, the Avnet kit provides Samtec technology to expand the capability “to connect, prototype, and deploy high performance RFSoC solutions on a single platform,” says Avnet.

The kit also includes an application called Avnet RFSoC Explorer for MATLAB and Simulink. Developed in partnership with MathWorks, the software provides signal capture and analysis with MATLAB and Simulink and offers radio-in-the-loop co-simulation over Gigabit Ethernet. It’s designed to work with MathWorks’ Free MATLAB Trial Package for Wireless Communications.

Further information

The Avnet RFSoC Development Kit is available for $9,495. More information may be found in Avnet’s announcement, as well as the product and shopping pages.

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