Reflex CES has introduced a system for the rapid design, validation, and verification of complex, high-density ASIC and SoC (system-on-chip) designs with up to 125-million gates.
The FPP25 development system is based on a prototyping board containing three Xilinx Virtex-7 FPGAs, controlled by embedded Linux running on a Freescale QorIQ microprocessor.
Key features of the prototyping board include:
- ASIC designs over 25 millions of equivalent logic gates
- Three on-board Virtex-7 FPGAs: 2x V2000T; 1 VX485T
- Up to 396 1.25GHz differential links between the three FPGAs
- Up to 8GB DDR3 SODIMM memories on each FPGA
- Extension board capabilities through 80 differential links @1.25Gbps using boards or cable
- Advanced Global Clock & Reset Configurable Networks
- Software for partitioning and verification
- Onboard Freescale QorIQ embedded microprocessor
- Supervision through 10/100/1000 Ethernet
- Data upload/download through PCIe x4 Gen2 cabling
- Run-time software with GUI, to control hardware
FPP25 block diagram
The FPP25 prototyping platform interfaces by means of gigabit Ethernet, USB, and cabled 4-lane PCIe. Each Virtex-7 2000T FPGA intercommunicates by nearly 400 LVDS signals at 1.25Gbps. The onboard Freescale QorIQ microprocessor (running embedded Linux) handles configuration and monitoring tasks.
As many as five FPP25 platforms can be chained together, for use in projects requiring up to 125 million ASIC gates. The FPP25 comes with design tools that support the required design, verification, and debug tasks.
For further details, visit Reflex CES’s website.