A non-profit company is developing an open source, 64-bit “lowRISC” SoC that will enable fully open hardware, “from the CPU core to the development board.”
University of Cambridge spinoff “lowRISC” is a not-for-profit company with a goal of making a completely open computing eco-system, including the instruction set architecture (ISA), processor silicon, and development boards. The first step is to develop a new system-on-chip design based on the new, 64-bit RISC-V ISA developed at the University of California, Berkeley.
Further goals listed by the project include:
- To create a fully open SoC and low-cost development board and to support the open-source hardware community. This will involve volume silicon manufacture.
- To explore and promote novel hardware security features
- To make it simple for existing companies and especially semiconductor startups to create derivative designs, e.g. by sharing scripts, tools, source, and our experience
- To create a benchmark design to aid academic research
The RISC-V design (see farther below) currently is sufficiently advanced that the lowRISC project can begin designing an SoC around it. So far, however, there are few details. “It’s early days to be honest, probably too early to give block diagrams, specs etc.,” wrote lowRISC team leader Robert Mullins in an email to LinuxGizmos.
RISC-V prototype silicon
(click to enlarge)
Mullins is a professor at the University of Cambridge, and was co-founder of the Raspberry Pi Foundation. The other team-members are Alex Bradbury, a frequent Raspberry Pi contributor working out of the same Computer Laboratory as Mullins, and Gavin Ferris of Dreamworks. There’s no formal relationship with the Pi Foundation, claims the lowRISC project.
An initial FPGA version of the SoC is expected in the next six months, with a test chip due for fabrication by the end of 2015. Tape out of production silicon is expected in late 2016 at the earliest.
Early versions of the SoC will not include a GPU. Initial clock-rate goals for the SoCs are 500MHz to 1GHz at 40nm and about 1.0-1.5GHz at 28nm. The SoC design will be released under BSD, a permissive open source license.
RISC-V: a new kind of ISA
Earlier this month, UC Berkeley’s Krste Asanović and David Patterson, leaders of the RISC-V project that forms the basis of lowRISC, posted a white paper on RISC-V, as well as a blog post in EETimes that summarizes the white paper. According to the paper, RISC-IV will initially target Linux-based Internet of Things (IoT) devices, with plans to spread throughout the computing spectrum.
Asanović is professor and director of the ASPIRE Lab at UC Berkeley that is leading the RISC-V project. Patterson, a professor of computer science at UC Berkeley, coined the term RISC (Reduced Instruction Set Computer) and helped develop the architecture back in the ’80s along with Carlo Sequin and others.
The authors pose a cogent argument for creating a new, fully open instruction set. The RISC-based ISAs in ARM, x86, MIPS, and Power architectures are controlled by companies that “have patents on quirks of their ISAs, which prevent others from using them without licenses,” write the authors. Licensing is expensive, so academics and smaller projects are shut out. Only about 10-15 companies have licenses, for example, that allow them to create custom ARM cores. “Licenses stifle competition and innovation by stopping many from designing and sharing their ISA-compatible cores,” they continue.
Other problems and inequities in the current system include the fact that the companies that own ISAs, such as ARM, Intel, IBM (Power), and Imagination Technologies (MIPS), depend on outsiders to write most of the software around the platforms, and yet these key stakeholders have no control over the ISAs themselves, say the authors.
There now exists in the larger open source community the talent to improve the ISAs and write new ones better than the gatekeeper companies can accomplish on their own, add the authors. A fully open ISA like RISC-V would encourage more free-market competition and innovation, faster time to market via open source methodology, and more affordable processors, they conclude.
One challenge with RISC-V and the lowRISC project built around it, is that there are already two open source RISC ISAs: SPARC and OpenRISC. Asanović and Patterson claim that only RISC-V meets all the requirements necessary for a competent open ISA, and that RISC-V has benefited from the example of SPARC and OpenRISC, learning from their mistakes. In addition, SPARC’s 64-bit address version (V9) is proprietary, and “OpenRISC may have lost momentum,” they add.
So far, UC Berkeley has developed eight silicon implementations of RISC-V, and there are external projects underway in India, the UK, and the US. Thanks in part to the open-source Chisel hardware design system, “one 64-bit RISC-V core is half the area, half the power, and faster than a 32-bit ARM core with a similar pipeline made in the identical process,” the authors claim.
This “Rocket” core “is about the same performance level as an ARM A5 when configured the same in the same process technology, but is 64-bit instead of 32-bit,” wrote Asanović in an email to LinuxGizmos. (See the project’s comparison data farther below.)
The screenshots below show the ANGEL RISC-V simulator booting to an ASH shell in Chrome on a Nexus 10 tablet. After the “Boot Linux” button is clicked, ANGEL downloads a 3MB Linux kernel and loads it into a simulated RISC-V processor.
ANGEL RISC-V simulator booting in Chrome on a Nexus 10
(click images to enlarge)
According to the project’s website, the ANGEL simulator running via Chrome implements an “RV64IMA” 64-bit RISC-V processor running in 10MB of memory, and executing roughly 1.5 million instructions per second. The simulator takes about 10 seconds to boot to ASH, after which you can issue BusyBox commands. (The simulator failed to trigger Android’s soft-keyboard on our Nexus 10, but on our Ubuntu desktop we could input BusyBox commands at the ASH prompt.)
RISC-V vs. Cortex-A5 smack-down
The RISC-V project has published a comparison between a 64-bit “Rocket” RISC-V core and ARM’s 32-bit Cortex-A5. Both cores offer single-instruction-issue, in-order pipelines, and both are implemented using the same TSMC process. Additionally, the Rocket provides “an MMU that supports page-based virtual memory” and optionally offers an IEEE 754-2008-compliant FPU, capable of both single- and double-precision floating-point operations, including “fused multiply-add,” says the project. The tabulated data shows that “the RISC-V core is faster, smaller, and uses less power,” states the project’s website.
|ARM Cortex-A5||RISC-V Rocket||RISC-V / ARM
|ISA register width||32 bits||64 bits||2|
|Frequency||> 1GHz||> 1GHz||1|
|Dhrystone performance||1.57 DMIPS/MHz||1.72 DMIPS/MHz||1.1|
|Area excluding caches||0.27 mm2||0.14 mm2||0.5|
|Area with 16KB caches||0.53 mm2||0.39 mm2||0.7|
|< 0.08||0.034||>= 0.4|
“We plan to open-source our Rocket core generator written in Chisel in the near future,” adds the project. “We are currently in the process of cleaning up the repository. Please stay tuned.”
More information on lowRISC may be found at the lowRISC.org website. The first RISC-V workshop will be held on January 14-15, 2015 in Monterey, Calif. A RISC-V boot camp will be held at the end of the workshop. More information about RISC-V is available at the RISC-V website.
(With additional reporting by Rick Lehrbaum.)