NXP’s i.MX8 X SoCs offer 2-4 Cortex-A35 cores, plus Cortex-M4F, Vivante, and Tensilica cores and safety features like ECC and SER.
At this week’s Embedded World show, NXP Semiconductors N.V. unveiled three dual- and quad-core Cortex-A35 based i.MX8 X SoCs. The new SoCs — the i.MX8 QuadXPlus, i.MX8 DualXPlus, and the i.MX8 DualX — also include Cortex-M4F MCUs, Vivante GPUs, and Tensilica DSPs, and feature ECC memory support, reduced soft-error-rate (SER) technology, and other industrial and automotive safety related features. We saw no mention of OS support, but the original i.MX8 SoCs support Linux, Android, FreeRTOS, QNX, Green Hills, and Dornerworks XEN.
i.MX8 X block diagram
(click image to enlarge)
Einhoven, Netherlands based NXP, which acquired Freescale and its i.MX6, QoriQ, and Kinetis product lines at the end of 2015, is now in the process of being acquired by Qualcomm. The deal still has some obstacles, and will not likely be completed until the end of the year.
NXP’s strength in automotive, which is a key application for the i.MX8 and other NXP chips, should help Qualcomm compete with Intel. This week Intel acquired Mobileye for $15.3 billion. The Israeli vision processing technology firm is expected to boost Intel’s self-driving car technology.
This week we also saw the first COM based on NXP’s i.MX6 ULL SoC. This cost-optimized version of the i.MX6 UL will arrive in the third quarter on a Toradex Colibri iMX6ULL module.
Inside the i.MX8 X
The new i.MX8 X platform, which was briefly mentioned in NXP’s October announcement of the three automotive focused i.MX8 Quad SoCs, is designed for industrial automation, HMI, industrial control, robotics, building control, automotive cluster, display audio infotainment, and telematics applications. Instead of using Cortex-A53 and -A72 cores like the i.MX8 Quad models, the i.MX8 X devices use slower, but more power efficient Cortex-A35 cores.
The first three i.MX8 X models are as follows:
- i.MX8 QuadXPlus — 4x Cortex-A35, 1x Cortex-M4F, 4-shader Vivante GPU, multi-format VPU, Tensilica HiFi 4 DSP
- i.MX8 DualXPlus — 2x Cortex-A35, 1x Cortex-M4F, 4-shader Vivante GPU, multi-format VPU, Tensilica HiFi 4 DSP
- i.MX8 DualX — 2x Cortex-A35, 1x Cortex-M4F, 2-shader Vivante GPU, multi-format VPU, Tensilica HiFi 4 DSP
By contrast, the three existing i.MX8 SoCs feature 4x Cortex-A53 cores, 2x Cortex-M4F MCUs, and 2x GC7000XS/VX GPUs. In addition, the QuadPlus model adds one high-end Cortex-A72 core, and the QuadMax, which was announced this week on a Toradex Apalis iMX8 COM, has two.
ARM’s Cortex-A35 design draws about 33 percent less power per core and occupies 25 percent less silicon area than Cortex-A53. The -A35 cores help the SoCs provide improved power efficiency, cooler operation, and longer battery life, says NXP. NXP did not mention clock rates, but Cortex-A35 cores can theoretically exceed 2GHz.
ARM Cortex-A35 architecture
(click image to enlarge)
The -A35 is not as power efficient as the new, IoT-focused Cortex-A32, which is slower, but smaller and more efficient, and uses a new, 32-bit-only ARMv8 architecture. The most notable role for the Cortex-A35 has been as as part of a low-power block of cores within MediaTek’s 10nm fabricated, deca-core Helio X30 SoC.
The i.MX8 X’s Cortex-A35 and -M4F cores are fabricated in a 28nm fully depleted silicon-on-insulator (FD-SOI) process that is said to “help the i.MX 8X run fanless in a hot environment without air flow. The FD-SOI process enables higher immunity to soft errors to improve mean time before failure (MTBF), as well as to “reduce latch-ups,” says NXP.
The i.MX8 X SoCs are notable for supporting Error Correcting Code (ECC) DDR3L-1866 RAM and L2 cache to guard against even a “single undetected memory bit flip.” The technology can “detect and correct memory corruption, greatly increasing the reliability and safety of industrial control systems,” says NXP. The SoCs also support LPDDR4-2400 RAM. Along with new reduced soft-error-rate (SER) and “increased latch-up immunity,” the ECC support helps the SoCs meet industrial Safety Integrity Level 3 (SIL 3) compliance, required in many industrial and automotive applications, says the company.
The SoCs offer a SafeAssure display controller with failover safety planes and a real-time domain that is independent of the Cortex-A35 and GPU, says the chipmaker. This is said to enable automotive safety certification of up to ASIL-B for cameras and displays.
Industrial safety certification is supported at up to SIL 3 “by leveraging ECC on the L2 cache and DDR3L memory interfaces, enabled by several popular commercial RTOS solutions from QNX, Green Hills and others,” says NXP. The failover display feature can detect a problem with the Cortex-A35 or GPU, and direct the Cortex-M4F chip to step in to display critical information until recovery.
i.MX8 X peripheral support
The i.MX8 X supports three simultaneous displays — two 1080p and one parallel WVGA — and can also decode a single 4K H.265 stream. The technology also supports “touchless interfaces” with audio processing and voice recognition technology, says NXP.
Multimedia peripheral support includes dual combo MIPI-DSI 4-lane interfaces and LVDS at up to 1080p. There’s also a 24-bit Parallel display interface at WXGA resolution. Camera support includes 4-lane MIPI-CSI2 and Parallel 8-bit CSI.
The SoCs support dual Ethernet ports, as well as SDIO 3.0 and eMMC 5.1. Other features include USB 3.0 OTG and USB 2.0 support, 3x CAN, 4x SPI, and 8x I2C (4x high- and 4x low-speed). Also onboard are PCIe, SPDIF, 12-bit ADC, and the automotive telematics focused MOST 25/50 interface.
Security features include AES-128 and RSA encryption, high assurance boot, and tamper detection. The SoCs are available in up to a -40 to 105°C range.
The i.MX8 QuadXPlus and i.MX8 DualXPlus will sample to initial customers in Q3 2017. There was no mention of the availability of the i.MX8 DualX. More information may be found on NXP’s i.MX8 X product page.