All News | Boards | Chips | Devices | Software | Archive | About | Contact | Subscribe
Follow LinuxGizmos:
Twitter Facebook Pinterest RSS feed
*   get email updates   *

Multi-core, Linux-ready RISC-V cores feature DSP

Mar 13, 2019 — by Eric Brown — 608 views

Andes unveiled new A25MP and AX25MP versions of its Linux-friendly A25 CPU cores claimed to be the first RISC-V cores with a “comprehensive” DSP. The 1GHz-plus cores provide cache coherency and support for SMP and up to quad-core designs.

At the RISC-V Workshop Taiwan, Andes Technology announced a second generation of its Linux-friendly, RISC-V ISA compatible A25 (32-bit) and AX25 (64-bit) CPU cores. The 32-bit, 28nm fabricated A25MP and 64-bit AX25MP are the first commercial RISC-V cores with comprehensive DSP instruction extensions, says Andes. Unlike the earlier A25 generation (see farther below), they are also the first to offer cache coherency for supporting multi-core and multi-processor support. The initial products, however, will be single-core designs.

The A25MP/AX25MP DSP (digital signal processor) ISA is based on the RISC-V P-extension draft (PDF) that Andes has donated to the RISC-V Foundation. DSPs are particularly useful in accelerating voice, audio, and image processing, says Taiwan-based Andes. The company also noted the capability to “empower applications such as artificial intelligence and Advanced Driver-Assistance Systems (ADAS).”

When used with the firm’s compiler, DSP libraries, and simulator, the A25MP/AX25MP DSPs “enable an over 7x times acceleration in the PNET for MtCNN (Multi-task Cascaded Convolutional Networks) face detection and alignment algorithm,” says Andes. The DSPs are also claimed to provide “an order of magnitude performance boost” on the CIFAR10 image classification benchmark for training machine learning and computer vision algorithms.

Andes CPU IP ecosystem (left) and architecture diagram for the Linux-ready A25/AX25 chips that form the foundation of the new A25MP and AX25MP
(click images to enlarge)

SoC designers can upgrade their existing, Linux-capable A25 and AX25 chips with the DSP ISA, says Andes. In addition, Andes announced a non-Linux capable, 32-bit D25F processor, “which is an A25 without MMU and S-mode support” that also offers the DSP ISA. All of Andes’ new processor IP’s “enjoy the same efficient baseline pipeline of the 25-series processors and the powerful ACE tools for custom instruction design,” says the company.

Andes’ earlier A25 and AX25

in Oct. 2018, Andes, which offers a wide range of MCU-like RISC processors, announced its first cores with the open source RISC-V ISA. These include its tiny, non-Linux compatible N22- and N25-series cores and its first Linux-ready RISC-V IP: the 32-bit A25 and 64-bit AX25.

There’s no documentation yet on the new DSP- and multi-core enabled A25MP and AX25MP, but they likely offer everything found on the similar, single-core, non-DSP A25 and AX25. Like Andes’ RISC-V-based N22- and N25-series cores, as well as earlier non RISC-V parts, the A25-series are part of an AndesCore family that “adopts RISC-V as the subset ” of its fifth generation AndeStar V5 architecture.

The A25 and AX25 appear to be almost identical except for their differing 32-bit vs. 64-bit architectures. The 64-bit AX25 supports high-performance embedded applications that require access address space over 4GB, says Andes. The only differences we saw in comparing their spec sheets was that the 64-bit AX25 is larger at 0.174 square millimeters vs 0.147, and it draws more dynamic power at 22uW/MHz vs 17.

Fabricated with the same TSMC 28nm HPC+ process as the new multi-core DSP models, the A25 and AX25 feature a 5-stage pipeline and support up to 1.2GHz, 3.5 CoreMark/MHz performance. The processor design supports single and double precision floating point instructions, half precision load/store, and an MMU and Supervisor Mode (S-Mode) for Linux based applications.

The A25 and AX25 provide branch prediction, Instruction and Data caches, local memories for low-latency accesses, and ECC support for L1 memory soft error protection. Other features include PLIC and vectored interrupts, AXI 64-bit or AHB 64/32-bit buses, and PowerBrake and WFI modes for low power and power management.

Development tools include an AndeSight IDE, a “COPILOT” tool for ACE, and JTAG and ICE debugging. Andes supplies AndesShape hardware development platforms for some of the AndesCore IP, but so far none of these support the A25 family.

The A25 and AX25 IP appear to be available to SoC designers, but it’s unclear if any A25-based SoCs have shipped as of yet. In January, the company announced that is cores had shipped in 1 billion SoCs in 2018, for a cumulative total of 3.5 billion. However, most, if not all, of these did not use RISC-V.

Other tuxified RISC-V chips

The A25 family of cores joins a small number of announced Linux-ready RISC-V cores, primarily from SiFive. The company has extended its cores into a Linux-friendly Freedom U540 SoC and has announced next-generation U74 and U74-MC designs.

Microchip’s Microsemi unit announced a Linux-friendly PolarFire SoC based in part on SiFive’s U54-MC cores. It’s billed as the world’s first RISC-V FPGA SOC. Another Linux-supported RISC-V chip is the Shakti chip, which is partially funded by the Indian government.

Further information

No availability information was provided by Andes Technology for the new A25MP and AX25MP RISC-V cores. More information may be found in its A25 and AX25 announcement.

(advertise here)

Print Friendly, PDF & Email

Please comment here...