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Linux-friendly TI SoC takes on FPGAs in DAQ apps

Apr 21, 2015 — by Eric Brown — 1,771 views
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TI’s Linux-ready 66AK2L06 SoC for high-speed data acquisition apps features dual Cortex-A15 cores, four DSPs, a digital front end, and a JESD204B interface.

The 66AK2L06 system-on-chip is the latest salvo by Texas Instruments in a long-running campaign to demonstrate that DSP-based SoCs can more efficiently and easily perform tasks typically done with FPGAs and ASICs. The Linux-supported 66AK2L06 aims to replace FPGAs with what it claims is an easier, cheaper, faster, and more power efficient way to directly connect to ADCs, DACs, and AFEs for high-speed data generation and acquisition. Applications are said to include avionics, defense, medical, and test and measurement equipment.

TI’s 66AK2L06 SoC eliminates the need for FPGAs and ASICs
(click image to enlarge)

Like many of the latest FPGAs from Altera and Xilinx, the TI SoC incorporates ARM Cortex cores, in this case dual Cortex-A15 cores at up to 1.2GHz. On the surface, the 66AK2L06 is just another in TI’s line of high end, ARM Cortex-A15 based Keystone II SoCs, such as the quad-core Cortex-A15 AM5K2Ex SoC. Like its earlier 66AK2Ex Keystone SoC and many other TI processors, the 66AK2L06 also integrates TI DSPs, in this case four programmable, 1.2GHz TMS320C66x chips.

Block diagrams: 66AK2L06 SoC (left) and Keystone II ARM CorePac
(click images to enlarge)

Yet, the 66AK2L06 is a radical departure from other Keystone SoCs due to its inclusion of a Digital Front End (DFE) and Digital Down Converter / Up Converter (DDUC), as well as a JESD204B interface. The latter, which complies with the JESD204B serial communications standard, connects directly to TI’s pre-validated analog-to-digital converters (ADCs), digital-to-analog converters (DAC), and analog front end (AFE).

66AK2L06 SoC’s integrated DFE functions
(click image to enlarge)

With the help of adaptive power technology, the 66AK2L06 draws up to 50 percent less power than competing devices with cooling requirements, says TI, presumably referring to leading FPGAs. The SoC enables integrated wideband sample rate conversion and digital filtering of up to 48 channels, thereby eliminating the need for an additional device, claims the chipmaker. This in turn is said to reduce the board footprint by up to 66 percent. The SoC delivers multichannel sampling rates up to 368Msps with 120MHz of processing bandwidth, says TI.

The programmable 66AK2L06 is touted for being much easier to develop for than FPGAs, enabling faster time to market. Developers can use software to change DFE configurations on the fly after deployment, and store multiple configurations in DDR or flash memory with the ability to switch dynamically, says TI. Thanks to the built-in DFE and JESD204B interfaces, developers can use software to change filters in a matter of days rather than weeks when using an FPGA, claims the company.

The DFE offers features including programmable DDC/DUC, FIR filters, “real or complex” I/O, front-end AGC, and an NCO/mixer, says TI. The DFE is said to enable functional resampling, noise and image filtering and shaping, I/Q modulation and demodulation, ADC dynamic range control, and center frequency conversion.

Interfacing via JESD204B to ADC and DAC chips
(click image to enlarge)

The SoC’s DSP cores have access to a Fast Fourier Transform Coprocessor (FFTC) module to accelerate the FFT and IFFT computations, which are used in applications including radar systems, says TI. A network coprocessor (NETCP) accelerator incorporates four gigabit Ethernet modules, as well as a packet accelerator (PA) to perform packet classification operations such as header matching and packet modification. The SoC also incorporates a security accelerator (SA) to encrypt and decrypt packets.

Typical application showing 66AK2L06 with companion chips
(click image to enlarge)

In addition to the DFE and JESD204B, the SoC provides the wide range of interfaces you would expect from a high end ARM-based SoC. Peripheral support includes dual PCIe x1 interfaces and 64 GPIOs, as well as four UART, three I2C, and three SPI interfaces. Single USB 3.0 and USIM interfaces are supported, along with other I/O.

The 66AK2L06 supports 72-bit DDR3 RAM at up to 1600MHz, and provides three EDMA controllers. The SoC is available in both commercial (0 to 100º) or extended (-40 to 100º) temperature versions.

66AK2L06 EVM with Linux-ready MCSDK
(click image to enlarge)

The 66AK2L06 is supported with a Linux-based Multicore Software Development Kit (MCSDK), as well as an RF Software Development Kit (RFSDK). The MCSDK kit supports TI’s SYS/BIOS for ARM cores in addition to open source Linux. An XEVMK2LX evaluation module will be available with the MCSDK and RFSDK, along with preloaded example projects.

Further information

The 66AK2L06 is currently sampling, and full volume availability will start in Q3 2015, says TI. More information, including a datasheet, schematics, and other documentation, may be found at the 66AK2L06 product page. The complete development setup, including the 66AK2L06 EVM board and Linux-enabled MCSDK, is available for $2095, says TI.

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