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Linux-driven RISC-V core to debut on an NXP i.MX SoC

Dec 11, 2019 — by Eric Brown — 2066 views

The OpenHW Group unveiled a Linux-driven “CORE-V Chassis” eval SoC due for tape-out in 2H 2020 based on an NXP i.MX SoC, but featuring its RISC-V and PULP-based 64-bit, 1.5GHz CV64A CPU and 32-bit CV32E cores. Meanwhile, Think Silicon demonstrated a RISC-V based NEOX|V GPU.

A not-for-profit, open source RISC-V initiative called the OpenHW Group that launched in June has announced that it plans to tape out a Linux-friendly CORE-V Chassis evaluation SoC in the second half of 2020 built around its 64-bit CV64A CPU core and 32-bit CV32E coprocessor. The RISC-V based cores will be integrated into an undefined, NXP i.MX heterogeneous, multi-core SoC design. The SoC was announced at this week’s RISC-V Summit in San Jose, Calif., where Think Silicon also demo’d an early version of a RISC-V-based NEOX|V GPU (see farther below).

The open source CV64A CPU core and 32-bit CV32E are based on RISC-V architecture PULP Platform cores developed by the University of ETH Zurich. The 64-bit CV64A core is based on ETH Zurich’s Ariane implementation of its RV64GC RISC-V core IP. RV64GC is also used by many other RISC-V projects, including SiFive’s U54.

PULP family generic architecture and overview
(click image to enlarge)
Source: ETH Zurich

The Ariane IP that forms the basis for the Linux-ready CV64A CPU core is a 6-stage, single issue, in-order CPU with M, S, and U privilege levels. Features include a configurable size, separate TLBs, a hardware PTW, and branch-prediction.

The Ariane supports FPGA emulation using Vivado on Digilent’s Xilinx Kintex-7 based Genesys 2 board. This was not mentioned in the CORE-V Chassis announcement, and there may well be another dev board in the works.

PULP Ariane architecture (left) and Open-ISA’s Vega board
(click images to enlarge)

The 32-bit CV32E coprocessor is based on ETH Zurich’s RI5CY implementation of its RV32IMFCXpulp RISC-V core IP, which is used by the PULPino MCU design. PULPino runs Zephyr on the ZedBoard PULPino, among other implementations. (The PULP project also offers a lower-end, 32-bit Ibex core IP that is not included in the CORE-V Chassis.) The current dev board for the CV32E is Open-ISA’s Arduino-compatible, Zephyr-supported Vega board.

NXP, which is a major backer of the project, will supply “the proven NXP i.MX platform,” complete with 3D and 2D GPUs and hardware security blocks. Peripheral support will include MIPI-DSI and -CSI, PCIe, GbE, USB 2.0, (LP)DDR4, multiple SDIO interfaces, and more.

“NXP is thrilled to be a key contributor to the CORE-V Chassis project leveraging our world class i.MX platform,” stated Rob Oshana, Chairman of the Board at OpenHW Group and VP Software Engineering at NXP.

In addition to NXP, the OpenHW Group members include Alibaba, Bluespec, CMC Microsystems, Embecosm, ETH Zurich, GreenWaves, Imperas, Metrics, Mythic, Onespin, Silicon Labs, and Thales. Imperas and Metrics are contributing a golden reference model and system Verilog simulator, respectively, for a Core-C Verification Test Bench Demo. OneSpin is providing its integrity verification solution for the project, and GreenWaves is integrating its low-power GAP8 AI chip.

UltraSoC joined the group in November, and on Dec. 6 announced it would contribute an open source version of its RISC-V trace encoder to the project. The OpenHW Group also has strategic partnerships with the Eclipse Foundation, among other organizations.

The CORE-V Chassis will form the basis of further multi-core evaluation SoCs, says the OpenHW Group. Presumably, some of these will begin to offer more open source IP in addition to the CPU cores. (See below for more on an emerging RISC-V-based NEOX|V GPU.)

There are numerous corporate and academic projects developing and releasing RISC-V based core IP, some of which run Linux. These include Andes Technology’s VPU-enabled AndesCore 27-series, which was also announced this week. There have been fewer full SoC designs, in part due to the lack of RISC-V based GPUs and other coprocessors that would enable a fully or even mostly open source SoC.

SiFive’s Linux-oriented SiFive Freedom U540 SoC, which runs on the HiFive Unleashed board, lacks GPUs or other typical SoC coprocessors. Microchips’s Linux-ready PolarFire SoC, which this week was released in an early access program similarly lacks media-oriented chips. However, it combines the same SiFive U54 cores with a RISC-V based PolarFire FPGA.
First RISC-V GPU core reaches demo stage
This week at the RISC-V Summit, Think Silicon is demonstrating an early preview of what it calls the first RISC-V ISA based 3D GPU IP. The low-power, 4-64 core NEOX|V design has a parallel multicore and multithreaded architecture based on the RISC-V64GC ISA instruction set “with adaptive NoC (Networks-on-Chip),” says Think Silicon.

The programmable NEOX|V has a variety of sizes and thread counts organized in up to 16 cluster elements. It offers cluster/core configurations that can achieve a total of 12.8 to 409.6 GFLOPS at 800MHz. The GPU supports FP16, FP32, and FP64 plus SIMD instructions. Machine learning and other AI algorithms will be supported.

For software, there will be Linux, RTOS, and Wear OS SDKs, with support for OpenGL ES and Vulkan via GLOVE middleware. Hardware evaluation platforms based on Xilinx SoC FPGAs will be available. No release date was listed.
Further information
The CORE-V Chassis evaluation SoC will enter tape-out in Q2 2020. More information may be found in the OpenHW Group’s CORE-V Chassis announcement and OpenHW Group website. Additional information may be found in slidedecks (PDF) from the June OpenHW Group launch announcement, here and here.

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