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Intel ditching tick-tock, shifting to three-stage CPU generations

Mar 23, 2016 — by Eric Brown — 1,692 views
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Starting with an upcoming 14nm “Kaby Lake” CPU, Intel will shift to three Core generations per fab process step, instead of two.

The “tick-tock” strategy Intel has been using for the last decade with its Core microprocessors has come to an end. Typically, Intel increases the fabrication density in a “tick” generation, such as 5th Generation Core “Broadwell” chips which debuted the 14-nanometer process, and then changes the architecture to exploit the new capabilities in better performance and lower power consumption in the “tock” release. In this case the tock would be the latest 6th Gen “Skylake” Core chips. Yet, as revealed in an SEC Form 10K filing (PDF) picked up by The Motley Fool, tick-tock is being replaced with a three-stage “Process-Architecture-Optimization” approach.

Intel diagram from SEC filing showing shift from tick tock to three-stage rollouts
(click image to enlarge)

The first example of the Optimization phase will be found in an upcoming “Kaby Lake” Core chip due later this year, which will maintain the 14nm process instead of moving to 10nm. In the 10-K brief, Intel says Kaby Lake will have “key performance advancements” compared to Skylake. The Motley Fool noted that leaks suggest the main focus will be on graphics and media.

Intel Kaby Lake Platform Overview
(click image to enlarge)

Hints of this shift came last July when Intel announced that 10nm fabrication production would be delayed into 2016 and that there would be a third 14nm Core family code-named “Kaby Lake.” As explained in an AnandTech report about that announcement, Intel then revealed that that the first 10nm chip, “Cannonlake” would be delayed from 2016 to 2017, and the unnamed “tock” 10nm architecture release would move from 2017 to 2018.

This change has now been confirmed as more than a temporary setback, but rather a new “Process-Architecture-Optimization” strategy going forward. “We expect to lengthen the amount of time we will utilize our 14nm and our next-generation 10nm process technologies, further optimizing our products and process technologies while meeting the yearly market cadence for product introductions,” says Intel in the filing.

Intel’s tick-tock cadence over recent generations
(click image to enlarge)

Intel’s abandonment of tick-tock is the clearest example yet that Moore’s Law is finally dead. The continual two-year cycle for doubling processor component density predicted by Intel cofounder Gordon Moore in 1975 has been expanding over the past decade to closer to 2.5 years, and is now heading for three years.

In one section of the filing, Intel says: “We continue executing to Moore’s Law by enabling new devices with higher functionality and complexity while controlling power, cost, and size.” Elsewhere, however, Intel says it will “relentlessly pursue Moore’s Law,” and the other two Moore’s Law citations use the past tense.

Intel’s shift also reflects the rise of ARM, which has made substantial inroads into Intel’s processor turf via optimization, despite lagging in fabrication density. As the laws of physics make it harder and harder to shrink components, and as mobile, embedded, and multimedia have changed the way we use processors, chipmakers are increasingly focusing on optimization. For example, new applications like computer vision and augmented and virtual reality are inspiring considerable optimization breakthroughs in graphics processor units (GPUs) and vice versa.

At the same, time Intel’s fab rivals such as TSMC, Samsung, and Global Foundries, which are used by ARM vendors, are accelerating their own fabrication technologies. For example, TSMC’s 7nm process, due to go into production in 2018, “should be very similar in terms of transistor density” to Intel’s 10nm technology, says The Motley Fool. For example, both are said to use Self-Aligned Quad Patterning for critical metal layers. Still, it appears that Intel will have a fabrication advantage for at least several more years.

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