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First MIPS Warrior processor targets device apps

Oct 14, 2013  |  Eric Brown
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Imagination Technologies announced its first MIPS “Warrior” processor, aimed at mobile, consumer, and embedded devices. The MIPS Series5 Warrior-P processor is equipped with six newly announced 32-bit MIPS P5600 cores said to offer up to twice the performance of earlier 32-bit cores, and features 128-bit SIMD, hardware virtualization, enhanced security, and Linux-focused memory addressing.

When U.K.-based Imagination Technologies announced its MIPS “Warrior” family of 32/64-bit processors, Android was prominently mentioned, but Linux was nowhere to be seen. In today’s announcement of its first Warrior processor, the Warrior-P, there’s no mention of Android, although several Linux-specific enhancements were noted. Imagination has yet to publish full specs on the processor — more details are due Oct. 17 — but it’s very likely Android is supported, as well as Linux.

The Warrior-P builds upon the MIPS Series5 architecture, and specifically the ProAptiv design, but it also debuts 32-bit MIPS P5600 cores featuring new virtualization and 128-bit SIMD functionality. The CPU is the first MIPS processor to be announced under the ownership of Imagination, which is known for its PowerVR GPUs. The company bought MIPS back in February of this year for $100 million.

The Warrior-P is designed for “next-generation mobile phones and tablets, connected consumer products such as set-top boxes, DTVs and multi-room multi-channel audio systems, and home and office networking and micro-servers,” says the company. Previous 32-bit MIPS processors have done well in the A/V categories, but never managed to make much headway in the mobile space.



Imagination’s MIPS product roadmap
(click image to enlarge)

 

Micro-servers, a category that ARM is also aggressively pursuing, is an entirely new playground for MIPS. Previously, 64-bit MIPS CPUs have been used in servers, although they’re more commonly found in high-end networking equipment, such as Cavium Octeon based systems.

Despite the Warrior name, military applications were not listed. We’re guessing the moniker has more to do with Imagination’s ambition to take on ARM in the CPU space. ARM wounded its fellow U.K. based partner when it abandoned PowerVR in favor of pushing its own Mali GPUs.

The Warrior-P is the high-end model out of three 32-bit processors based on the P5600 core. Future products include a mid-range Warrior-I processor based on the InterAptiv design, and an entry-level Warrior-M chip based on the MicroAptiv family. Over the next year, Imagination plans to introduce a line of 64-bit Warrior processors.



MIPS microAptiv microcontroller and microprocessor cores (with MMU)
(click images to enlarge)

 

Like some earlier 32-bit Series5 cores, the P5600 is fabricated in a 28-nanometer process. However, as explained in a statement by Tom Halfhill of The Linley Group, the P5600 is the “first MIPS core to implement the MIPS Release 5 ISA, which includes important features like the MIPS SIMD Architecture and virtualization.” The P5600 cores can be clocked from 1GHz to 2GHz, and in the Warrior-P design can be clustered in configurations of up to six cores.
 

128-bit SIMD: MIPS gets its own NEON

The P5600 is primarily notable for its 128-bit SIMD (single instruction, multiple data) processing technology, which should greatly improve MIPS support for multimedia. The technology is similar to that provided by the 128-bit NEON technology found in ARM Cortex processors. The SIMD engine improves the performance of “data-parallel applications such as audio codecs, image processing, DSP, low-level simple 2D graphics and other media-rich applications,” says Imagination.



MIPS P5600 block diagram
(click image to enlarge)

 

The SIMD engine is deployed as 32 architectural registers, each offering 128-bit throughput, and supports data types ranging from 8-bit integer to native double precision floating point, says Imagination. The engine can be “easily” supported with high-level languages like C or OpenCL, and supports code portability using JITs and other forms of dynamic compilers, says the company.
 

Security, virtualization, and Linux-ready memory addressing

Other major P5600 features include some undefined security technology, as well as the first hardware virtualization functionality found in a MIPS core. The virtualization implementation not only supports server and automotive computing, but is also designed for “entry level” applications, says the company.

The P5600 is touted for its advanced memory addressing features, including an Extended Physical Addressing (XPA) scheme said to enable access to physical memory beyond the 32-bit limit, all the way up to 1TB (40-bits). There’s also an Enhanced Virtual Addressing (EVA) technology touted as offering more flexible usage of virtual address space, including “easy and efficient use of memory for larger footprint Linux implementations.” Specifically, EVA allows user and kernel space to access more than 3GB each without the need for HIGHMEM support in Linux.

Additional P5600 enhancements are said to include widened datapaths and buses, increased L2 cache prefetching, and enhanced load/store bonding. The core also provides optimizations for JIT and browser applications, says Imagination.
 

Up to twice as fast as earlier 32-bit cores

The P5600 exceeds 3.5 CoreMark/MHz performance with 3.5 DMIPS/MHz, according to Imagination’s benchmarks. The core is said to deliver 1.2x to 2x performance of earlier 32-bit Series5 cores based on SPECint2000, Linpack, and Javascript/Browser tests. It also provides 2x to 3x faster data movement on widely-used routines such as MemCopy libraries, claims the company.

The P5600′s silicon footprint is said to be 30 percent smaller than the ARM cores used in the eight-core Samsung Exynos 5 Octa. Presumably, this means it’s also smaller than earlier MIPS 32-bit cores. No claims were made regarding power efficiency, which has always been a relative strength of the MIPS platform, compared to say, Intel’s x86.

The Warrior-P processors are said to be binary compatible with other Series5 CPUs. Imagination is also working on toolchain development for the processor. The improvements include “advanced” support for gcc and proprietary compilers, as well as enhancements to Imagination’s Codescape debuggers, says the company.

The P5600 core, and presumably the Warrior-P processor design, will be available for licensing by the end of the year, says Imagination Technologies. More information will be presented at the 2013 Linley Tech Processor Conference in Santa Clara, Calif. For now, all we have is the Warrior-P press release.
 

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