AMD unveiled a lower-powered version of the Ryzen Embedded V1000 SoC called the Ryzen Embedded R1000 with dual quad-threaded cores, 12-25W TDPs, triple 4K displays, and support for dual 10GbE ports.
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Wave Computing has released its first open source MIPS ISA without license fees or royalties. The MIPS Open release includes the latest R6 version of the MIPS 32-and-64-bit ISA plus an IDE for embedded Linux and RTOSes and support for the free MIPSfpga core.
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Esperanto, Google, SiFive, and Western Digital announced an LF-hosted “CHIPS Alliance” to curate and develop open source code for RISC-V chip development, including WD’s donated SweRV core. Meanwhile, Intel is open sourcing its PCIe-based CXL interconnect.
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Andes unveiled new A25MP and AX25MP versions of its Linux-friendly A25 CPU cores claimed to be the first RISC-V cores with a “comprehensive” DSP. The 1GHz-plus cores provide cache coherency and support for SMP and up to quad-core designs.
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Congatec announced a “Conga-B7E3” COM Express Type 7 module that runs Linux or Windows on AMD’s up to 16-core Epyc Embedded 3000 with up to 96GB DDR4, 4x 10GbE networking, 32x PCIe lanes, and an optional 1TB NVMe disk.
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NXP unveiled a Linux-friendly i.MX8M Nano SoC with the same up to 4x 14nm Cortex-A53 cores as the faster, pin-compatible i.MX8M Mini, but with no VPU and a 600MHz Cortex-M7 instead of an -M4.
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Octavo unveiled an “OSD32MP1” System-in-Package (SiP) version of ST’s new dual -A7 STM32MP1 SoC. It matches the SoC’s 18 x 18mm footprint while adding 1GB DDR3, a PMIC, EEPROM, oscillators, and passives.
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Renesas unveiled an “RZ-G2” family of up to octa-core Cortex-A53 and -A57 SoCs with an updated RZ/G Linux Platform with the 64-bit Arm CIP SLTS kernel for 10 year+ availability. There are also two 96Boards dev boards.
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[Updated: Feb. 23] — ST unveiled a Linux-driven “STM32MP1” SoC with dual Cortex-A7 cores and a Cortex-M4 core. The SoC will be available in April with several Raspberry Pi compatible dev boards.
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Allied Vision’s Alvium embedded cameras include 1500 (MIPI-CSI) and 1800 (CSI and USB3) models, both with On Semi sensors at up 2592 × 1944 and V4L2 drivers that support Jetson and i.MX6/8 dev boards.
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Intel is phasing out its lightweight Quark processors, with final orders wrapping up this summer, and shipments ending in 2022. The Quark suffered from growing competition from high-end MCUs and low-end Cortex-A7 chips and the lack of a clear market focus.
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Wave Computing will follow in RISC-V’s path by offering its MIPS ISA as “open source” code without royalties or proprietary licensing. The MIPS Open initiative will focus on the development of SoCs for emerging IoT edge applications.
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Phytec’s “phyCore-AM65x SOM” and dev kit runs Linux on TI’s new AM65x SoC, which combines 4x Cortex-A53 cores, a PowerVR GPU, 2x Cortex-R5F MCUs, and 6x real-time PRU chips that support up to 6x TSN capable GbE ports.
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Microchip’s Microsemi unit unveiled a low power, real-time deterministic “PolarFire SoC” architecture for Linux edge devices that combines its PolarFire FPGA with 4x RISC-V CPU cores supplied by SiFive.
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