Broadcom is sampling a system-on-chip (SOC) aimed at control-plane and edge-networking devices. The StrataGX BCM58525 is equipped with a dual-core 1.2GHz ARM Cortex-A9 processor, and features a packet-buffer subsystem, gigabit Ethernet PHY, cryptographic and programmable packet-handling accelerators, and a Linux development kit.
Broadcom’s StrataGX BCM58525 is said to be 20 percent faster than previous StrataGX SOCs. Existing systems include the BCM53010 and BCM53014 (single-core Cortex-A9 at 800MHz), BCM53011 and BCM53015 (dual-core Cortex-A9 at 800MHz), BCM53012 and BCM53016 (dual-core Cortex-A9 at 1GHz), and BCM53017 and BCM53018 (dual-core Cortex-A9 at 1.1GHz).
The StrataGX BCM58525 is designed for switching control and management, enterprise access points, and residential router/gateways, says Broadcom. It supports network edge and aggregation layer applications including cloud-based services like video conferencing, collaboration, and surveillance, says Broadcom. In networking lingo, the control plane handles routing, security, applications, and other user-facing services, while the data plane interfaces with broadband telecom pipes, and handles high-speed switching, quality of service, and packet header parsing.
Broadcom BCM58525 block diagram
According to Broadcom, the BCM58525′s dual-core Cortex-A9 processor is backed by a 32KB four-way set associative instruction cache and a 32KB four-way set associative data cache. The SOC also integrates a network acceleration engine with fixed and programmable engines, plus BroadSync HD and time-sync hardware. A built-in network acceleration engine performs L2/L3/L4 packet classification, traffic quality of service (QoS) assignment, and DMA, and the chip also supports both IEEE 802 AV bridging and IEEE 1588 standards. On-chip peripheral interfaces and controllers include a Gigabit Ethernet PHY, MACsec, SGMII, DDR2/3 memory, PCIe Gen-2, USB 3.0 and 2.0, serial and NAND flash, SDIO3, audio/voice TDM subsystems. Additional I/O controllers and interfaces include JTAG, UART, BSCa, MDIO, GPIO, and SPI.
The StrataGX BCM58525 is equipped with the following key features:
- Dual-core ARM Cortex-A9, clocked up to 1.2GHz
- Gigabit Ethernet PHYs
- Programmable accelerator for offloading packet handling tasks from CPU to achieve “line-rate performance”
- Cryptographic accelerator for 2Gbps IPsec performance
- IEEE MAC Security (MACsec)
- Dedicated packet buffer subsystem, said to speed aggregate processor speed by 20 percent or more
- Common architecture with StrataConnect/StrataXGS, enabling software re-use
- Linux development kit (LDK)
- Reference design including schematics, tools and software
Broadcom’s StrataGX BCM58525 Series SOCs are now sampling, with volume production slated for Q4 2013. A reference design platform is also said to be available now. More information may be found at Broadcom’s BCM58525 product page.