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ARM/FPGA hybrid SoC taps Cortex-A53, 14nm process

Oct 29, 2013  |  Eric Brown
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Altera announced a new high-end ARM/FPGA Stratix SoC, and also the first processor to be manufactured with Intel’s 14nm 3D Tri-Gate process. The Linux-friendly Stratix 10 SX SoC will incorporate a quad-core 64-bit ARM Cortex-A53 subsystem integrated with floating-point DSP blocks and gigahertz-speed FPGA fabric that offers twice the core performance of previous Stratix FPGAs, claims Altera.

Designed for data center computing acceleration, radar systems, and communications infrastructure, as well as other high-end embedded applications, the Stratix 10 SX SoC will be offered along with two variants that lack its Cortex-A53 “hard processor system” (HPC). These include the Stratix 10 GT FPGA and the lower-cost, more power efficient Stratix 10 GX FPGA.

The Stratix 10 SX SoC follows in the pathway of Altera’s Cyclone V SX, which like the rival Xilinx Zynq-7000, combines FPGA and Cortex-A9 subsystems, tightly linked by a high-speed AXI interconnect. The Stratix 10 SX SoC, however, offers a much more powerful ARM subsystem with its 64-bit Cortex-A53 platform. This is one of the first fully announced Cortex-A53 system-on-chips, although Apple’s currently shipping A7 and AppliedMicro’s X-Gene are based on the same basic A53/A57 architecture.

Many more Cortex-A53 and faster, higher-core-count A57 SoCs are expected over the next year or two including Nvidia’s Project Denver (Tegra 6), Cavium’s Project Thunder, Freescale’s QorIQ LS2, and a follow-on to Samsung’s Exynos 5. The A53 has been billed primarily as a power-efficient mobile SoC while the A57 is more of a server and high-end networking platform, but there appears to be quite a bit of overlap. Both flavors are available in Big.Little combination SoCs similar to today’s Cortex-A7/A15 hybrids like the Exynos 5 Octa.

The Stratix 10 SX SoC offers much faster FPGA circuitry than the Cyclone V and other FPGA-only Stratix, Arria, and Cyclone processors. The programmable-logic performance is said to be higher than 1GHz, or two times the core performance of current high-end 28nm FPGAs. The Stratix 10 SX SoC will achieve more than six times more data throughput “compared to today’s highest performing SoC FPGAs,” says Altera. The SoC also provides 10 TFLOPs of single-precision floating-point DSP performance, says Altera.
 

First SoC out of the 14nm Tri-Gate

In large part the performance increase is due to the use of Intel’s 14nm 3D Tri-Gate process, which also applies to the Cortex-A53 subsystem. The Stratix 10 is the first 14nm Tri-Gate chip, as even Intel’s 4th Generation Core (“Haswell”) processors use 22nm with the Tri-Gate process.

No clock rate was supplied for the quad-core Cortex-A53 subsystem, except to say the SoC as a whole represents the “first gigahertz FPGAs and SoCs,” according to Altera. As for power efficiency, the SoC provides 70 percent lower power consumption than “prior high-end FPGAs and SoCs.” This presumably refers to the Arria 10 SoC, which offers dual 1.5GHz Cortex-A9 cores, compared to the 800MHz cores on the Cyclone V SoC, and offers higher-end FPGA circuitry.



Power consumption of Stratix 10 vs Arria 10 and other Altera processors
(click image to enlarge; source: Altera)

 

The Cortex-A53 subsystem also offers virtualization support, as well as 256TB memory reach and error correction code (ECC) on L1 and L2 caches. The cores can run in 32-bit mode, letting them run Cortex-A9 operating systems and code unmodified, and providing an upgrade path from Altera’s 28nm and 20nm SoC FPGAs, says the company.

Selected highlights of the Stratix 10 SX SoC include:

  • 2x the core performance of prior generation high-end FPGAs
  • > 10 TFLOPs of single-precision floating-point DSP performance
  • > 4x processor data throughput of prior-generation SoCs
  • 4x serial transceiver bandwidth from previous FPGAs (28Gbps backplane for switching, 56Gbps chip-to-chip/module for edge interface)
  • Over 2.5Tbps bandwidth for serial memory with support for Hybrid Memory Cube
  • Over 1.3Tbps bandwidth for parallel memory interfaces with support for DDR4 at 3200Mbps
  • Largest monolithic FPGA device (>4M logic elements)
  • Heterogeneous multi-die 3D solutions including SRAM, DRAM, and ASICs
  • 70% lower power consumption than prior high-end FPGAs and SoCs
  • 100GFlops/Watt of single-precision floating point efficiency
  • Complementary Enpirion PowerSoC power IC chips
  • “Fastest compile times in the industry”

Altera did not offer many specifics on the architecture, although according to an EE Times report it appears to offer a greater degree of integration than running a high-speed AXI interconnect between subsystems, as is done on the Cyclone V SoC. The device is architected in layers, says the story, with the Cortex-A53 layer on top, which performs “high-level tasks like load-balancing, flow control, secure boot, and FPGA configuration and power management.” This is followed by the DSP layer, used for floating point configurations and waveform processing. Below this is the FPGA logic layer, which handles deep packet inspection, hardware acceleration, and special cryptographic engines tasks.

No OS support details were announced for the Stratix 10 SX SoC, but considering the Cyclone V SoC’s Linux support, Linux seems like a sure bet. In fact, Altera says the SoC will provide “software compatibility and a common ARM ecosystem of tools and operating system support” with previous Altera ARM/FPGA hybrids, including the Cyclone 5 and Arria 10. The SoC will also ship with Altera’s SoC Embedded Design Suite (EDS), featuring ARM’s Development Studio 5 (DS-5), and will also include Altera’s OpenCL SDK.

News Electronics interviewed Altera senior VP Danny Biran, who said that his company had considered using a Big.Little configuration with dual Cortex-A53 and dual Cortex-A57 cores, but found it “less attractive” than a quad-core A53 approach. “The A57 has a larger die because of more pipeline stages and is less power efficient,” Biran was quoted as saying.

Altera did not note a timeline for the Stratix 10 SX SoC, but EE Times says Intel’s fabrication of the chips will begin in 2014. More information may be found at the Altera Stratix 10 product page.
 

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One Response to “ARM/FPGA hybrid SoC taps Cortex-A53, 14nm process”

  1. GeorgeV says:

    Denver is most likely custom CPU core, not Cortex A57, at least from everything Nvidia has said so far.

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